[LLVMdev] Why do X86_32TargetMachine and X86_64TargetMachine classes exist?
Jim Grosbach
grosbach at apple.com
Tue Jan 7 10:23:01 PST 2014
LGTM
-Jim
On Jan 7, 2014, at 8:21 AM, David Woodhouse <dwmw2 at infradead.org> wrote:
> On Mon, 2014-01-06 at 15:00 -0800, Jim Grosbach wrote:
>>
>> Cool. I have no objection to merging them. Seems the right thing to do
>> IMO.
>
> Looks like this...
>
> --
> David Woodhouse Open Source Technology Centre
> David.Woodhouse at intel.com Intel Corporation
> From 9161fc70377f8f004144b654cc3ca5c9a22e0279 Mon Sep 17 00:00:00 2001
> From: David Woodhouse <David.Woodhouse at intel.com>
> Date: Tue, 7 Jan 2014 16:13:21 +0000
> Subject: [PATCH 1/2] [x86] Kill gratuitous X86_{32,64}TargetMachine
> subclasses, use X86TargetMachine
>
> ---
> lib/Target/X86/X86Subtarget.cpp | 6 +--
> lib/Target/X86/X86Subtarget.h | 2 +-
> lib/Target/X86/X86TargetMachine.cpp | 51 +++++++------------------
> lib/Target/X86/X86TargetMachine.h | 76 ++++++-------------------------------
> 4 files changed, 29 insertions(+), 106 deletions(-)
>
> diff --git a/lib/Target/X86/X86Subtarget.cpp b/lib/Target/X86/X86Subtarget.cpp
> index 5ee986c..b183ed0 100644
> --- a/lib/Target/X86/X86Subtarget.cpp
> +++ b/lib/Target/X86/X86Subtarget.cpp
> @@ -551,14 +551,14 @@ void X86Subtarget::initializeEnvironment() {
>
> X86Subtarget::X86Subtarget(const std::string &TT, const std::string &CPU,
> const std::string &FS,
> - unsigned StackAlignOverride, bool is64Bit)
> + unsigned StackAlignOverride)
> : X86GenSubtargetInfo(TT, CPU, FS)
> , X86ProcFamily(Others)
> , PICStyle(PICStyles::None)
> , TargetTriple(TT)
> , StackAlignOverride(StackAlignOverride)
> - , In64BitMode(is64Bit)
> - , In32BitMode(!is64Bit)
> + , In64BitMode(TargetTriple.getArch() == Triple::x86_64)
> + , In32BitMode(TargetTriple.getArch() == Triple::x86)
> , In16BitMode(false) {
> initializeEnvironment();
> resetSubtargetFeatures(CPU, FS);
> diff --git a/lib/Target/X86/X86Subtarget.h b/lib/Target/X86/X86Subtarget.h
> index f39389e..1e9fba8 100644
> --- a/lib/Target/X86/X86Subtarget.h
> +++ b/lib/Target/X86/X86Subtarget.h
> @@ -220,7 +220,7 @@ public:
> ///
> X86Subtarget(const std::string &TT, const std::string &CPU,
> const std::string &FS,
> - unsigned StackAlignOverride, bool is64Bit);
> + unsigned StackAlignOverride);
>
> /// getStackAlignment - Returns the minimum alignment known to hold of the
> /// stack frame on entry to the function and which must be maintained by every
> diff --git a/lib/Target/X86/X86TargetMachine.cpp b/lib/Target/X86/X86TargetMachine.cpp
> index 9fa2481..462dae3 100644
> --- a/lib/Target/X86/X86TargetMachine.cpp
> +++ b/lib/Target/X86/X86TargetMachine.cpp
> @@ -24,11 +24,11 @@ using namespace llvm;
>
> extern "C" void LLVMInitializeX86Target() {
> // Register the target.
> - RegisterTargetMachine<X86_32TargetMachine> X(TheX86_32Target);
> - RegisterTargetMachine<X86_64TargetMachine> Y(TheX86_64Target);
> + RegisterTargetMachine<X86TargetMachine> X(TheX86_32Target);
> + RegisterTargetMachine<X86TargetMachine> Y(TheX86_64Target);
> }
>
> -void X86_32TargetMachine::anchor() { }
> +void X86TargetMachine::anchor() { }
>
> static std::string computeDataLayout(const X86Subtarget &ST) {
> // X86 is little endian
> @@ -69,49 +69,22 @@ static std::string computeDataLayout(const X86Subtarget &ST) {
> return Ret;
> }
>
> -X86_32TargetMachine::X86_32TargetMachine(const Target &T, StringRef TT,
> - StringRef CPU, StringRef FS,
> - const TargetOptions &Options,
> - Reloc::Model RM, CodeModel::Model CM,
> - CodeGenOpt::Level OL)
> - : X86TargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, false),
> - DL(computeDataLayout(*getSubtargetImpl())),
> - InstrInfo(*this),
> - TLInfo(*this),
> - TSInfo(*this),
> - JITInfo(*this) {
> - initAsmInfo();
> -}
> -
> -void X86_64TargetMachine::anchor() { }
> -
> -X86_64TargetMachine::X86_64TargetMachine(const Target &T, StringRef TT,
> - StringRef CPU, StringRef FS,
> - const TargetOptions &Options,
> - Reloc::Model RM, CodeModel::Model CM,
> - CodeGenOpt::Level OL)
> - : X86TargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, true),
> - // The x32 ABI dictates the ILP32 programming model for x64.
> - DL(computeDataLayout(*getSubtargetImpl())),
> - InstrInfo(*this),
> - TLInfo(*this),
> - TSInfo(*this),
> - JITInfo(*this) {
> - initAsmInfo();
> -}
> -
> /// X86TargetMachine ctor - Create an X86 target.
> ///
> X86TargetMachine::X86TargetMachine(const Target &T, StringRef TT,
> StringRef CPU, StringRef FS,
> const TargetOptions &Options,
> Reloc::Model RM, CodeModel::Model CM,
> - CodeGenOpt::Level OL,
> - bool is64Bit)
> + CodeGenOpt::Level OL)
> : LLVMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL),
> - Subtarget(TT, CPU, FS, Options.StackAlignmentOverride, is64Bit),
> + Subtarget(TT, CPU, FS, Options.StackAlignmentOverride),
> FrameLowering(*this, Subtarget),
> - InstrItins(Subtarget.getInstrItineraryData()){
> + InstrItins(Subtarget.getInstrItineraryData()),
> + DL(computeDataLayout(*getSubtargetImpl())),
> + InstrInfo(*this),
> + TLInfo(*this),
> + TSInfo(*this),
> + JITInfo(*this) {
> // Determine the PICStyle based on the target selected.
> if (getRelocationModel() == Reloc::Static) {
> // Unless we're in PIC or DynamicNoPIC mode, set the PIC style to None.
> @@ -135,6 +108,8 @@ X86TargetMachine::X86TargetMachine(const Target &T, StringRef TT,
> // default to hard float ABI
> if (Options.FloatABIType == FloatABI::Default)
> this->Options.FloatABIType = FloatABI::Hard;
> +
> + initAsmInfo();
> }
>
> //===----------------------------------------------------------------------===//
> diff --git a/lib/Target/X86/X86TargetMachine.h b/lib/Target/X86/X86TargetMachine.h
> index 174d391..03c366e 100644
> --- a/lib/Target/X86/X86TargetMachine.h
> +++ b/lib/Target/X86/X86TargetMachine.h
> @@ -30,32 +30,38 @@ namespace llvm {
> class StringRef;
>
> class X86TargetMachine : public LLVMTargetMachine {
> + virtual void anchor();
> X86Subtarget Subtarget;
> X86FrameLowering FrameLowering;
> InstrItineraryData InstrItins;
> + const DataLayout DL; // Calculates type size & alignment
> + X86InstrInfo InstrInfo;
> + X86TargetLowering TLInfo;
> + X86SelectionDAGInfo TSInfo;
> + X86JITInfo JITInfo;
>
> public:
> X86TargetMachine(const Target &T, StringRef TT,
> StringRef CPU, StringRef FS, const TargetOptions &Options,
> Reloc::Model RM, CodeModel::Model CM,
> - CodeGenOpt::Level OL,
> - bool is64Bit);
> + CodeGenOpt::Level OL);
>
> + virtual const DataLayout *getDataLayout() const { return &DL; }
> virtual const X86InstrInfo *getInstrInfo() const {
> - llvm_unreachable("getInstrInfo not implemented");
> + return &InstrInfo;
> }
> virtual const TargetFrameLowering *getFrameLowering() const {
> return &FrameLowering;
> }
> virtual X86JITInfo *getJITInfo() {
> - llvm_unreachable("getJITInfo not implemented");
> + return &JITInfo;
> }
> virtual const X86Subtarget *getSubtargetImpl() const{ return &Subtarget; }
> virtual const X86TargetLowering *getTargetLowering() const {
> - llvm_unreachable("getTargetLowering not implemented");
> + return &TLInfo;
> }
> virtual const X86SelectionDAGInfo *getSelectionDAGInfo() const {
> - llvm_unreachable("getSelectionDAGInfo not implemented");
> + return &TSInfo;
> }
> virtual const X86RegisterInfo *getRegisterInfo() const {
> return &getInstrInfo()->getRegisterInfo();
> @@ -74,64 +80,6 @@ public:
> JITCodeEmitter &JCE);
> };
>
> -/// X86_32TargetMachine - X86 32-bit target machine.
> -///
> -class X86_32TargetMachine : public X86TargetMachine {
> - virtual void anchor();
> - const DataLayout DL; // Calculates type size & alignment
> - X86InstrInfo InstrInfo;
> - X86TargetLowering TLInfo;
> - X86SelectionDAGInfo TSInfo;
> - X86JITInfo JITInfo;
> -public:
> - X86_32TargetMachine(const Target &T, StringRef TT,
> - StringRef CPU, StringRef FS, const TargetOptions &Options,
> - Reloc::Model RM, CodeModel::Model CM,
> - CodeGenOpt::Level OL);
> - virtual const DataLayout *getDataLayout() const { return &DL; }
> - virtual const X86TargetLowering *getTargetLowering() const {
> - return &TLInfo;
> - }
> - virtual const X86SelectionDAGInfo *getSelectionDAGInfo() const {
> - return &TSInfo;
> - }
> - virtual const X86InstrInfo *getInstrInfo() const {
> - return &InstrInfo;
> - }
> - virtual X86JITInfo *getJITInfo() {
> - return &JITInfo;
> - }
> -};
> -
> -/// X86_64TargetMachine - X86 64-bit target machine.
> -///
> -class X86_64TargetMachine : public X86TargetMachine {
> - virtual void anchor();
> - const DataLayout DL; // Calculates type size & alignment
> - X86InstrInfo InstrInfo;
> - X86TargetLowering TLInfo;
> - X86SelectionDAGInfo TSInfo;
> - X86JITInfo JITInfo;
> -public:
> - X86_64TargetMachine(const Target &T, StringRef TT,
> - StringRef CPU, StringRef FS, const TargetOptions &Options,
> - Reloc::Model RM, CodeModel::Model CM,
> - CodeGenOpt::Level OL);
> - virtual const DataLayout *getDataLayout() const { return &DL; }
> - virtual const X86TargetLowering *getTargetLowering() const {
> - return &TLInfo;
> - }
> - virtual const X86SelectionDAGInfo *getSelectionDAGInfo() const {
> - return &TSInfo;
> - }
> - virtual const X86InstrInfo *getInstrInfo() const {
> - return &InstrInfo;
> - }
> - virtual X86JITInfo *getJITInfo() {
> - return &JITInfo;
> - }
> -};
> -
> } // End llvm namespace
>
> #endif
> --
> 1.8.4.2
>
> From 3cd6dd8799bbf7ea6f328ec493812187e5255c98 Mon Sep 17 00:00:00 2001
> From: David Woodhouse <David.Woodhouse at intel.com>
> Date: Mon, 6 Jan 2014 21:07:05 +0000
> Subject: [PATCH 2/2] Add x86_16 target
>
> ---
> include/llvm/ADT/Triple.h | 1 +
> lib/Support/Triple.cpp | 10 +++++++-
> lib/Target/X86/AsmParser/X86AsmParser.cpp | 1 +
> lib/Target/X86/MCTargetDesc/X86MCTargetDesc.cpp | 32 +++++++++++++++++++++----
> lib/Target/X86/MCTargetDesc/X86MCTargetDesc.h | 2 +-
> lib/Target/X86/TargetInfo/X86TargetInfo.cpp | 5 +++-
> lib/Target/X86/X86AsmPrinter.cpp | 1 +
> lib/Target/X86/X86Subtarget.cpp | 2 +-
> lib/Target/X86/X86TargetMachine.cpp | 1 +
> 9 files changed, 46 insertions(+), 9 deletions(-)
>
> diff --git a/include/llvm/ADT/Triple.h b/include/llvm/ADT/Triple.h
> index 314ee4e..633c6c4 100644
> --- a/include/llvm/ADT/Triple.h
> +++ b/include/llvm/ADT/Triple.h
> @@ -65,6 +65,7 @@ public:
> thumb, // Thumb: thumb, thumbv.*
> x86, // X86: i[3-9]86
> x86_64, // X86-64: amd64, x86_64
> + x86_16, // X86-16: 16-bit mode (equivalent to .code16gcc)
> xcore, // XCore: xcore
> nvptx, // NVPTX: 32-bit
> nvptx64, // NVPTX: 64-bit
> diff --git a/lib/Support/Triple.cpp b/lib/Support/Triple.cpp
> index 273316a..8acf319 100644
> --- a/lib/Support/Triple.cpp
> +++ b/lib/Support/Triple.cpp
> @@ -38,6 +38,7 @@ const char *Triple::getArchTypeName(ArchType Kind) {
> case thumb: return "thumb";
> case x86: return "i386";
> case x86_64: return "x86_64";
> + case x86_16: return "x86_16";
> case xcore: return "xcore";
> case nvptx: return "nvptx";
> case nvptx64: return "nvptx64";
> @@ -79,7 +80,8 @@ const char *Triple::getArchTypePrefix(ArchType Kind) {
> case systemz: return "systemz";
>
> case x86:
> - case x86_64: return "x86";
> + case x86_64:
> + case x86_16: return "x86";
>
> case xcore: return "xcore";
>
> @@ -181,6 +183,7 @@ Triple::ArchType Triple::getArchTypeForLLVMName(StringRef Name) {
> .Case("thumb", thumb)
> .Case("x86", x86)
> .Case("x86-64", x86_64)
> + .Case("x86-16", x86_16)
> .Case("xcore", xcore)
> .Case("nvptx", nvptx)
> .Case("nvptx64", nvptx64)
> @@ -199,6 +202,7 @@ const char *Triple::getArchNameForAssembler() {
> return StringSwitch<const char*>(getArchName())
> .Case("i386", "i386")
> .Case("x86_64", "x86_64")
> + .Case("x86_16", "x86_16")
> .Case("powerpc", "ppc")
> .Case("powerpc64", "ppc64")
> .Case("powerpc64le", "ppc64le")
> @@ -223,6 +227,7 @@ static Triple::ArchType parseArch(StringRef ArchName) {
> // FIXME: Do we need to support these?
> .Cases("i786", "i886", "i986", Triple::x86)
> .Cases("amd64", "x86_64", "x86_64h", Triple::x86_64)
> + .Cases("x86_16", "i8086", "i86", Triple::x86_16)
> .Case("powerpc", Triple::ppc)
> .Cases("powerpc64", "ppu", Triple::ppc64)
> .Case("powerpc64le", Triple::ppc64le)
> @@ -688,6 +693,7 @@ static unsigned getArchPointerBitWidth(llvm::Triple::ArchType Arch) {
> case llvm::Triple::tce:
> case llvm::Triple::thumb:
> case llvm::Triple::x86:
> + case llvm::Triple::x86_16:
> case llvm::Triple::xcore:
> case llvm::Triple::spir:
> return 32;
> @@ -744,6 +750,7 @@ Triple Triple::get32BitArchVariant() const {
> case Triple::tce:
> case Triple::thumb:
> case Triple::x86:
> + case Triple::x86_16:
> case Triple::xcore:
> // Already 32-bit.
> break;
> @@ -793,6 +800,7 @@ Triple Triple::get64BitArchVariant() const {
> case Triple::nvptx: T.setArch(Triple::nvptx64); break;
> case Triple::ppc: T.setArch(Triple::ppc64); break;
> case Triple::sparc: T.setArch(Triple::sparcv9); break;
> + case Triple::x86_16:
> case Triple::x86: T.setArch(Triple::x86_64); break;
> case Triple::spir: T.setArch(Triple::spir64); break;
> }
> diff --git a/lib/Target/X86/AsmParser/X86AsmParser.cpp b/lib/Target/X86/AsmParser/X86AsmParser.cpp
> index 3ed20d9..c2cde2e 100644
> --- a/lib/Target/X86/AsmParser/X86AsmParser.cpp
> +++ b/lib/Target/X86/AsmParser/X86AsmParser.cpp
> @@ -2759,6 +2759,7 @@ bool X86AsmParser::ParseDirectiveCode(StringRef IDVal, SMLoc L) {
>
> // Force static initialization.
> extern "C" void LLVMInitializeX86AsmParser() {
> + RegisterMCAsmParser<X86AsmParser> W(TheX86_16Target);
> RegisterMCAsmParser<X86AsmParser> X(TheX86_32Target);
> RegisterMCAsmParser<X86AsmParser> Y(TheX86_64Target);
> }
> diff --git a/lib/Target/X86/MCTargetDesc/X86MCTargetDesc.cpp b/lib/Target/X86/MCTargetDesc/X86MCTargetDesc.cpp
> index 9d5ff10..0fdd9de 100644
> --- a/lib/Target/X86/MCTargetDesc/X86MCTargetDesc.cpp
> +++ b/lib/Target/X86/MCTargetDesc/X86MCTargetDesc.cpp
> @@ -48,8 +48,12 @@ std::string X86_MC::ParseX86Triple(StringRef TT) {
> std::string FS;
> if (TheTriple.getArch() == Triple::x86_64)
> FS = "+64bit-mode,-32bit-mode,-16bit-mode";
> - else
> + else if (TheTriple.getArch() == Triple::x86)
> FS = "-64bit-mode,+32bit-mode,-16bit-mode";
> + else if (TheTriple.getArch() == Triple::x86_16)
> + FS = "-64bit-mode,-32bit-mode,+16bit-mode";
> + else
> + llvm_unreachable("no valid arch type");
> return FS;
> }
>
> @@ -402,58 +406,76 @@ static MCInstrAnalysis *createX86MCInstrAnalysis(const MCInstrInfo *Info) {
> // Force static initialization.
> extern "C" void LLVMInitializeX86TargetMC() {
> // Register the MC asm info.
> - RegisterMCAsmInfoFn A(TheX86_32Target, createX86MCAsmInfo);
> - RegisterMCAsmInfoFn B(TheX86_64Target, createX86MCAsmInfo);
> + RegisterMCAsmInfoFn A(TheX86_16Target, createX86MCAsmInfo);
> + RegisterMCAsmInfoFn B(TheX86_32Target, createX86MCAsmInfo);
> + RegisterMCAsmInfoFn C(TheX86_64Target, createX86MCAsmInfo);
>
> // Register the MC codegen info.
> - RegisterMCCodeGenInfoFn C(TheX86_32Target, createX86MCCodeGenInfo);
> - RegisterMCCodeGenInfoFn D(TheX86_64Target, createX86MCCodeGenInfo);
> + RegisterMCCodeGenInfoFn D(TheX86_16Target, createX86MCCodeGenInfo);
> + RegisterMCCodeGenInfoFn E(TheX86_32Target, createX86MCCodeGenInfo);
> + RegisterMCCodeGenInfoFn F(TheX86_64Target, createX86MCCodeGenInfo);
>
> // Register the MC instruction info.
> + TargetRegistry::RegisterMCInstrInfo(TheX86_16Target, createX86MCInstrInfo);
> TargetRegistry::RegisterMCInstrInfo(TheX86_32Target, createX86MCInstrInfo);
> TargetRegistry::RegisterMCInstrInfo(TheX86_64Target, createX86MCInstrInfo);
>
> // Register the MC register info.
> + TargetRegistry::RegisterMCRegInfo(TheX86_16Target, createX86MCRegisterInfo);
> TargetRegistry::RegisterMCRegInfo(TheX86_32Target, createX86MCRegisterInfo);
> TargetRegistry::RegisterMCRegInfo(TheX86_64Target, createX86MCRegisterInfo);
>
> // Register the MC subtarget info.
> + TargetRegistry::RegisterMCSubtargetInfo(TheX86_16Target,
> + X86_MC::createX86MCSubtargetInfo);
> TargetRegistry::RegisterMCSubtargetInfo(TheX86_32Target,
> X86_MC::createX86MCSubtargetInfo);
> TargetRegistry::RegisterMCSubtargetInfo(TheX86_64Target,
> X86_MC::createX86MCSubtargetInfo);
>
> // Register the MC instruction analyzer.
> + TargetRegistry::RegisterMCInstrAnalysis(TheX86_16Target,
> + createX86MCInstrAnalysis);
> TargetRegistry::RegisterMCInstrAnalysis(TheX86_32Target,
> createX86MCInstrAnalysis);
> TargetRegistry::RegisterMCInstrAnalysis(TheX86_64Target,
> createX86MCInstrAnalysis);
>
> // Register the code emitter.
> + TargetRegistry::RegisterMCCodeEmitter(TheX86_16Target,
> + createX86MCCodeEmitter);
> TargetRegistry::RegisterMCCodeEmitter(TheX86_32Target,
> createX86MCCodeEmitter);
> TargetRegistry::RegisterMCCodeEmitter(TheX86_64Target,
> createX86MCCodeEmitter);
>
> // Register the asm backend.
> + TargetRegistry::RegisterMCAsmBackend(TheX86_16Target,
> + createX86_32AsmBackend);
> TargetRegistry::RegisterMCAsmBackend(TheX86_32Target,
> createX86_32AsmBackend);
> TargetRegistry::RegisterMCAsmBackend(TheX86_64Target,
> createX86_64AsmBackend);
>
> // Register the object streamer.
> + TargetRegistry::RegisterMCObjectStreamer(TheX86_16Target,
> + createMCStreamer);
> TargetRegistry::RegisterMCObjectStreamer(TheX86_32Target,
> createMCStreamer);
> TargetRegistry::RegisterMCObjectStreamer(TheX86_64Target,
> createMCStreamer);
>
> // Register the MCInstPrinter.
> + TargetRegistry::RegisterMCInstPrinter(TheX86_16Target,
> + createX86MCInstPrinter);
> TargetRegistry::RegisterMCInstPrinter(TheX86_32Target,
> createX86MCInstPrinter);
> TargetRegistry::RegisterMCInstPrinter(TheX86_64Target,
> createX86MCInstPrinter);
>
> // Register the MC relocation info.
> + TargetRegistry::RegisterMCRelocationInfo(TheX86_16Target,
> + createX86MCRelocationInfo);
> TargetRegistry::RegisterMCRelocationInfo(TheX86_32Target,
> createX86MCRelocationInfo);
> TargetRegistry::RegisterMCRelocationInfo(TheX86_64Target,
> diff --git a/lib/Target/X86/MCTargetDesc/X86MCTargetDesc.h b/lib/Target/X86/MCTargetDesc/X86MCTargetDesc.h
> index 41ae435..6febed2 100644
> --- a/lib/Target/X86/MCTargetDesc/X86MCTargetDesc.h
> +++ b/lib/Target/X86/MCTargetDesc/X86MCTargetDesc.h
> @@ -30,7 +30,7 @@ class Target;
> class StringRef;
> class raw_ostream;
>
> -extern Target TheX86_32Target, TheX86_64Target;
> +extern Target TheX86_16Target, TheX86_32Target, TheX86_64Target;
>
> /// DWARFFlavour - Flavour of dwarf regnumbers
> ///
> diff --git a/lib/Target/X86/TargetInfo/X86TargetInfo.cpp b/lib/Target/X86/TargetInfo/X86TargetInfo.cpp
> index 815d235..4e89c25 100644
> --- a/lib/Target/X86/TargetInfo/X86TargetInfo.cpp
> +++ b/lib/Target/X86/TargetInfo/X86TargetInfo.cpp
> @@ -12,9 +12,12 @@
> #include "llvm/Support/TargetRegistry.h"
> using namespace llvm;
>
> -Target llvm::TheX86_32Target, llvm::TheX86_64Target;
> +Target llvm::TheX86_16Target, llvm::TheX86_32Target, llvm::TheX86_64Target;
>
> extern "C" void LLVMInitializeX86TargetInfo() {
> + RegisterTarget<Triple::x86_16, /*HasJIT=*/true>
> + W(TheX86_16Target, "x86-16", "16-bit X86: Pentium-Pro and above");
> +
> RegisterTarget<Triple::x86, /*HasJIT=*/true>
> X(TheX86_32Target, "x86", "32-bit X86: Pentium-Pro and above");
>
> diff --git a/lib/Target/X86/X86AsmPrinter.cpp b/lib/Target/X86/X86AsmPrinter.cpp
> index 5bd58c5..6c1f3ec 100644
> --- a/lib/Target/X86/X86AsmPrinter.cpp
> +++ b/lib/Target/X86/X86AsmPrinter.cpp
> @@ -718,6 +718,7 @@ void X86AsmPrinter::EmitEndOfAsmFile(Module &M) {
>
> // Force static initialization.
> extern "C" void LLVMInitializeX86AsmPrinter() {
> + RegisterAsmPrinter<X86AsmPrinter> W(TheX86_16Target);
> RegisterAsmPrinter<X86AsmPrinter> X(TheX86_32Target);
> RegisterAsmPrinter<X86AsmPrinter> Y(TheX86_64Target);
> }
> diff --git a/lib/Target/X86/X86Subtarget.cpp b/lib/Target/X86/X86Subtarget.cpp
> index b183ed0..cc8935b 100644
> --- a/lib/Target/X86/X86Subtarget.cpp
> +++ b/lib/Target/X86/X86Subtarget.cpp
> @@ -559,7 +559,7 @@ X86Subtarget::X86Subtarget(const std::string &TT, const std::string &CPU,
> , StackAlignOverride(StackAlignOverride)
> , In64BitMode(TargetTriple.getArch() == Triple::x86_64)
> , In32BitMode(TargetTriple.getArch() == Triple::x86)
> - , In16BitMode(false) {
> + , In16BitMode(TargetTriple.getArch() == Triple::x86_16) {
> initializeEnvironment();
> resetSubtargetFeatures(CPU, FS);
> }
> diff --git a/lib/Target/X86/X86TargetMachine.cpp b/lib/Target/X86/X86TargetMachine.cpp
> index 462dae3..1a903b8 100644
> --- a/lib/Target/X86/X86TargetMachine.cpp
> +++ b/lib/Target/X86/X86TargetMachine.cpp
> @@ -24,6 +24,7 @@ using namespace llvm;
>
> extern "C" void LLVMInitializeX86Target() {
> // Register the target.
> + RegisterTargetMachine<X86TargetMachine> W(TheX86_16Target);
> RegisterTargetMachine<X86TargetMachine> X(TheX86_32Target);
> RegisterTargetMachine<X86TargetMachine> Y(TheX86_64Target);
> }
> --
> 1.8.4.2
>
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