[LLVMdev] Question about per-operand machine model

[jingu]

>Resources and latency are not tied. An instruction is mapped to a scheduling class. A scheduling class is mapped to a set of resources and a per-operand list of latencies.

Thanks for your kind explanation.

Our heuristic algorithm have needed the latency and the resource per operand to check resource conflicts per cycle. In order to support this with LLVM, I expected a per-operand list of resources like latencies with a scheduling class.

Can I ask you something to modify on tablegen? I think that the 'WriteResourceID' field of 'MCWriteLatencyEntry' is for identifying the WriteResources of each defintion as commented on code. As you know, tablegen sets the 'WriteResourceID' field of 'MCWriteLatencyEntry' with 'WriteID' when the 'Write' of defition is referenced by a 'ReadAdvance'. If we always set this field with 'WriteID', it causes problem? I can see that 'ReadAdvance' only uses the 'WriteResourceID' field of 'MCWriteLatencyEntry' in 'computeOperandLatency' function. I think the pair of latency and write resource for defintion will be useful to check conflicts of resources. As reference, I have attached simple patch.

Thanks,
JinGu Kang

-------------- next part --------------
Index: utils/TableGen/SubtargetEmitter.cpp
===================================================================
--- utils/TableGen/SubtargetEmitter.cpp	(revision 201607)
+++ utils/TableGen/SubtargetEmitter.cpp	(working copy)
@@ -932,12 +932,7 @@
       WLEntry.Cycles = 0;
       unsigned WriteID = WriteSeq.back();
       WriterNames.push_back(SchedModels.getSchedWrite(WriteID).Name);
-      // If this Write is not referenced by a ReadAdvance, don't distinguish it
-      // from other WriteLatency entries.
-      if (!SchedModels.hasReadOfWrite(
-            SchedModels.getSchedWrite(WriteID).TheDef)) {
-        WriteID = 0;
-      }
+
       WLEntry.WriteResourceID = WriteID;