[LLVMdev] selecting ISD node - help

[DaAn]

Hey, I wanted to add an intrinsics to read MSRs.

So I added the intrinsics and lowered it to a new ISD node I created
ISD::RDMSR, its first operand is the MSR id.

I added a case in X86DAGToDAGISel::Select for ISD::RDMSR.
Now I know rdmsr works like so:
  mov r/ecx, <id>
  rdmsr
  r/eax holds the lower 32/64 bit

>From what I understood this needs a Token Factor node, nodes which are
dependent on each other?
  case X86ISD::RDMSR:
  {  
	  unsigned idReg;
	  SDValue idRegValue;
	  unsigned resultReg;

	  SDLoc dl = SDLoc(Node);

	  SDValue id = Node->getOperand(0);
	  EVT resultType = Node->getValueType(0);

	  if(Subtarget->is64Bit())
	  {
		  idReg = X86::RCX;
		  resultReg = X86::RAX;
	  }
	  else
	  {
		  idReg = X86::ECX;
		  resultReg = X86::EAX;
	  }

	  idRegValue = CurDAG->getRegister(idReg, resultType);

	  SmallVector<SDValue, 8> Ops;

	  SDValue setIdNode = CurDAG->getCopyToReg(CurDAG->getEntryNode(), dl,
idRegValue, id, SDValue());
	  SDValue rdmsrNode = SDValue(CurDAG->getMachineNode(X86::RDMSR, dl,
MVT::Other, setIdNode), 0);
	  SDValue resultNode = CurDAG->getCopyFromReg(rdmsrNode, dl, resultReg,
resultType);

	  Ops.push_back(resultNode);
	  Ops.push_back(rdmsrNode);
	  Ops.push_back(setIdNode);

	  SDValue ResultValue = CurDAG->getNode(ISD::TokenFactor, dl, resultType,
&Ops[0], Ops.size());
	  
	  return ResultValue.getNode();
  }

But when I run this I get:
Assertion failed: I != VRBaseMap.end() && "Node emitted out of order -
late", file ..\..\..\..\lib\CodeGen\SelectionDAG\InstrEmitter.cpp, line 292

I know that I can just do this using in-line assembly instead of an
intrinsics but I want to learn a bit about LLVM development so I though
doing this (which I need anyway) will be a good way.
I'm pretty new to LLVM and I tried searching for the answer, but maybe I
misunderstood the answers or didn't find the correct post or code to look
at.
Help will be greatly appreciated. Thanks in advance.





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