[LLVMdev] Generating code for target with immediate constant?

Thomson lilotom at gmail.com
Tue Dec 23 19:17:41 PST 2014


To generate code for a target which doesn't have immediate constant as
instruction operand, do I (the target specific back-end, XXXTarget) need to
provide code to break up the SDNode with constant (like ISD::ADD $reg1, #1)
to 2 SDNodes (ISD::LOAD $reg2, #1; ISD::ADD $reg1, $reg2) in my
XXXTargetLowering::LowerOperation, or LLVM target-independent framework can
do such transformation automatically with my instruction pattern definition?

Thanks
-Thomson
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