[LLVMdev] instruction/intrinsic for segmented adressing

[Tim Northover]

(Adding llvmdev to CC again)

On 5 December 2014 at 10:21, mobi phil <mobi at mobiphil.com> wrote:
>>
>> Probably fairly minimal in most cases (on x86). On ARM there is
>> definitely a cost.
>>
> hm... why? You cannot have indexed addressing?

The code that needs to be emitted is roughly:
    [..."segment"-offset into x1...]
    mrs x0, tpidr_el0
    ldr xD, [x0, x1]

That's a more complex addressing mode and an additional MRS
instruction over the usual sequence. You also lose the ability to fold
the actual address-computation into the LDR.

> and now the obvious question: for aarch64, is there an adrspace(256)
> identical declaration for LLVM?

Nope. That's what I meant by saying there's no direct control over
these features from LLVM.

> I am completely lost, where and how to start the transformation. One
> solution would be to modify clang code generation... but that seems to be
> more complex solution and not so general solution.

It's a very difficult problem. The main issue is that the stack won't
be in this special address space (at least not without heavy LLVM
modifications), so you need a way to distinguish stack accesses from
heap. Without source annotation that's reducible to the halting
problem. For example:

int load_address(int *addr) {
  return addr;
}

int evil(int *heap_addr) {
  int local_var = 42;
  return load_address(rand() % 2 ? heap_addr : &local_var);
}

Should the code emitted for load_address use gs or not?

Cheers.

Tim.