[LLVMdev] instruction/intrinsic for segmented adressing

[Tim Northover]

Hi,

> Now on x64 I have GS/FS registers. Pitty enough their addresses can be
> changed only by the OS (not in user space). Not sure what "tools" are
> available on ARM, hopefully there is something.

There are no segment registers on ARM. AArch64 has a couple of thread
pointer registers that might be abused for the purpose (one even
writable from user-space). AArch32 only has one, I believe, which is
usually claimed by the OS for threads.

>  New my question is, what is the best  way to tell LLVM to generate [FS:xxx]
> and/or [GS:xxxx] class of instructions?

On x86, the addrspace(N) property of pointers triggers use of segment
registers (256 => gs, 257 => fs by the looks of it). E.g.

define i32 @foo(i32 addrspace(256)* %addr) {
  %val = load i32 addrspace(256)* %addr
  ret i32 %val
}

But as in the ARM case, this is usually the mechanism used for
thread-local storage, so be careful.

Cheers.

Tim.