[LLVMdev] Unnecessary reload of register

Thu Aug 28 09:57:48 PDT 2014

Hi all,
I'm trying to figure out why llvm(llvm 3.1, can't easilly try it with other
version) inserts an unnecessary load for one register.

The following is the code before instruction selection:
----------------------------------------------------------------------------
    %call = tail call i32 @_Z7zahlIntv()
    %0 = inttoptr i32 %call to i32*
    %1 = load i32* %0, align 4, !tbaa !0
    %arrayidx1 = getelementptr inbounds i32* %0, i32 1
    %2 = load i32* %arrayidx1, align 4, !tbaa !0
    %mul = mul nsw i32 %2, %1
    ret i32 %mul
----------------------------------------------------------------------------

After instruction selection I get the following:

----------------------------------------------------------------------------
  BB#0: derived from LLVM BB %entry
   ADJCALLSTACKDOWN 8, %SP<imp-def,dead>, %SP<imp-use>
   JSUB <ga:@_Z7zahlIntv>, 1, <fi#-2>, 0, <fi#0>, 0, ...
   ADJCALLSTACKUP 8, 0, %SP<imp-def,dead>, %SP<imp-use>
   %vreg0<def> = LDrid <fi#-2>, 4; mem:LD4[FixedStack-2] AkkuDRegs:%vreg0
   %vreg2<def> = COPY %vreg0; PointerAdrRegs:%vreg2 AkkuDRegs:%vreg0
   %vreg1<def> = LDridAddr %vreg2, 4; mem:LD4[%arrayidx1](tbaa=!"int")
AkkuDRegs:%vreg1 PointerAdrRegs:%vreg2
   %vreg4<def> = COPY %vreg0; PointerAdrRegs:%vreg4 AkkuDRegs:%vreg0
   %vreg3<def> = MULINTDLDridAddr %vreg1<kill>, %vreg4, 0;
mem:LD4[%0](tbaa=!"int") AkkuDRegs:%vreg3,%vreg1 PointerAdrRegs:%vreg4
   STrid <fi#-, 0, %vreg3<kill>; mem:ST4[FixedStack-1] AkkuDRegs:%vreg3
----------------------------------------------------------------------------

So far everything seems to look fine. But I don't understand why there is a
%vreg4 as it has the same value as %vreg2.

At the end I get the following:

----------------------------------------------------------------------------
   JSUB <ga:@_Z7zahlIntv>, 1, %SP, 24, %SP, 0, %AKKU1D<imp-def,dead>,
%AR2<imp-def,dead>
   %AKKU1D<def> = LDrid %SP, 28; mem:LD4[FixedStack-2]
   STrid %SP, 8, %AKKU1D<kill>
   %AKKU1D<def> = LDrid %SP, 8
   %AR2<def> = LAR2d %AKKU1D<kill>
   %AKKU1D<def> = LDridAddr %AR2<kill>, 4; mem:LD4[%arrayidx1](tbaa=!"int")
   STrid %SP, 12, %AKKU1D<kill>
   %AKKU1D<def> = LDrid %SP, 8
   %AR2<def> = LAR2d %AKKU1D<kill>
   %AKKU1D<def> = LDrid %SP, 12
   %AKKU1D<def> = MULINTDLDridAddr %AKKU1D<kill>, %AR2<kill>, 0;
mem:LD4[%0](tbaa=!"int")
   STrid %SP, 0, %AKKU1D<kill>; mem:ST4[FixedStack-1]
----------------------------------------------------------------------------

It should be obvious that the second "  %AR2<def> = LAR2d %AKKU1D<kill>" is
unneccessary. I've no idea why llvm thinks it needs to fill the register
with the prober value again. No instruction in the whole block is
destroying the value in AR2. Might it be because %AR2 is marked kill in the
LDridAddr instruction? If so, how can I mark the instruction that it isn't
destroying the register value? The following is the definition of the
instruction:

----------------------------------------------------------------------------

def MEMirPtr : Operand<i32> {

let PrintMethod = "printMemOperand";

let MIOperandInfo = (ops PointerAdrRegs, i64imm);

}

class AwlInst<dag outs, dag ins, string asmstr, list<dag> pattern, int size
= 0> : Instruction {

 field bits<32> Inst;

 let Namespace = "Awl0";

 dag OutOperandList = outs;

 dag InOperandList = ins;

 let AsmString = asmstr;

 let Pattern = pattern;

 let Size = size;

}

def LDridAddr : AwlInst<(outs AkkuDRegs:$dst), (ins MEMirPtr:$addr),

"L D$addr; \t// LDridAddr $addr -> $dst",

[(set AkkuDRegs:$dst, (load addraddr:$addr))], 4>;

----------------------------------------------------------------------------

The complete output of print-after-all is attached to this mail.

Any hints are appreciated.

Thanks in advance,

Markus
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-------------- next part --------------
  *** IR Dump After Preliminary module verification ***
  define i32 @main() {
  entry:
    %call = tail call i32 @_Z7zahlIntv()
    %0 = inttoptr i32 %call to i32*
    %1 = load i32* %0, align 4, !tbaa !0
    %arrayidx1 = getelementptr inbounds i32* %0, i32 1
    %2 = load i32* %arrayidx1, align 4, !tbaa !0
    %mul = mul nsw i32 %2, %1
    ret i32 %mul
  }
  *** IR Dump After Module Verifier ***
  define i32 @main() {
  entry:
    %call = tail call i32 @_Z7zahlIntv()
    %0 = inttoptr i32 %call to i32*
    %1 = load i32* %0, align 4, !tbaa !0
    %arrayidx1 = getelementptr inbounds i32* %0, i32 1
    %2 = load i32* %arrayidx1, align 4, !tbaa !0
    %mul = mul nsw i32 %2, %1
    ret i32 %mul
  }
  *** IR Dump After Lower Garbage Collection Instructions ***
  define i32 @main() {
  entry:
    %call = tail call i32 @_Z7zahlIntv()
    %0 = inttoptr i32 %call to i32*
    %1 = load i32* %0, align 4, !tbaa !0
    %arrayidx1 = getelementptr inbounds i32* %0, i32 1
    %2 = load i32* %arrayidx1, align 4, !tbaa !0
    %mul = mul nsw i32 %2, %1
    ret i32 %mul
  }
  *** IR Dump After Remove unreachable blocks from the CFG ***
  define i32 @main() {
  entry:
    %call = tail call i32 @_Z7zahlIntv()
    %0 = inttoptr i32 %call to i32*
    %1 = load i32* %0, align 4, !tbaa !0
    %arrayidx1 = getelementptr inbounds i32* %0, i32 1
    %2 = load i32* %arrayidx1, align 4, !tbaa !0
    %mul = mul nsw i32 %2, %1
    ret i32 %mul
  }
  *** IR Dump After Optimize for code generation ***
  define i32 @main() {
  entry:
    %call = tail call i32 @_Z7zahlIntv()
    %0 = inttoptr i32 %call to i32*
    %1 = load i32* %0, align 4, !tbaa !0
    %arrayidx1 = getelementptr inbounds i32* %0, i32 1
    %2 = load i32* %arrayidx1, align 4, !tbaa !0
    %mul = mul nsw i32 %2, %1
    ret i32 %mul
  }
  *** IR Dump After Insert stack protectors ***
  define i32 @main() {
  entry:
    %call = tail call i32 @_Z7zahlIntv()
    %0 = inttoptr i32 %call to i32*
    %1 = load i32* %0, align 4, !tbaa !0
    %arrayidx1 = getelementptr inbounds i32* %0, i32 1
    %2 = load i32* %arrayidx1, align 4, !tbaa !0
    %mul = mul nsw i32 %2, %1
    ret i32 %mul
  }
  *** IR Dump After Preliminary module verification ***
  define i32 @main() {
  entry:
    %call = tail call i32 @_Z7zahlIntv()
    %0 = inttoptr i32 %call to i32*
    %1 = load i32* %0, align 4, !tbaa !0
    %arrayidx1 = getelementptr inbounds i32* %0, i32 1
    %2 = load i32* %arrayidx1, align 4, !tbaa !0
    %mul = mul nsw i32 %2, %1
    ret i32 %mul
  }
  *** IR Dump After Module Verifier ***
  define i32 @main() {
  entry:
    %call = tail call i32 @_Z7zahlIntv()
    %0 = inttoptr i32 %call to i32*
    %1 = load i32* %0, align 4, !tbaa !0
    %arrayidx1 = getelementptr inbounds i32* %0, i32 1
    %2 = load i32* %arrayidx1, align 4, !tbaa !0
    %mul = mul nsw i32 %2, %1
    ret i32 %mul
  }
  # *** IR Dump After Expand ISel Pseudo-instructions ***:
  # Machine code for function main: SSA
  Frame Objects:
    fi#-2: size=4, align=1, fixed, at location [SP]
    fi#-1: size=1, align=1, fixed, at location [SP+4]
    fi#0: size=8, align=1, at location [SP]

  BB#0: derived from LLVM BB %entry
  	ADJCALLSTACKDOWN 8, %SP<imp-def,dead>, %SP<imp-use>
  	JSUB <ga:@_Z7zahlIntv>, 1, <fi#-2>, 0, <fi#0>, 0, ...
  	ADJCALLSTACKUP 8, 0, %SP<imp-def,dead>, %SP<imp-use>
  	%vreg0<def> = LDrid <fi#-2>, 4; mem:LD4[FixedStack-2] AkkuDRegs:%vreg0
  	%vreg2<def> = COPY %vreg0; PointerAdrRegs:%vreg2 AkkuDRegs:%vreg0
  	%vreg1<def> = LDridAddr %vreg2, 4; mem:LD4[%arrayidx1](tbaa=!"int") AkkuDRegs:%vreg1 PointerAdrRegs:%vreg2
  	%vreg4<def> = COPY %vreg0; PointerAdrRegs:%vreg4 AkkuDRegs:%vreg0
  	%vreg3<def> = MULINTDLDridAddr %vreg1<kill>, %vreg4, 0; mem:LD4[%0](tbaa=!"int") AkkuDRegs:%vreg3,%vreg1 PointerAdrRegs:%vreg4
  	STrid <fi#-, 0, %vreg3<kill>; mem:ST4[FixedStack-1] AkkuDRegs:%vreg3
  	RET_JMPmain