[LLVMdev] Pseudo load and store instructions for AArch64

[Sergey Dmitrouk]

Hi Renato,

> > I'm trying to add pseudo 64-bit load and store instructions for AArch64, which
> > should have latencies set to "1" while being otherwise exactly the same as
> > normal load and store instructions.
> 
> Can I ask why would you need that?

This is the only way I found to stop Machine Instruction Scheduler from
reordering load and store instructions.  I asked on this specific topic
several times before, but no one answered.  The following approaches
didn't work in this case:

 - different kind of chaining;
 - gluing;
 - single pseudo instruction for load and store as it needs temporary
   register, but such pseudos are expanded after RA.

It's needed to make code of inlined memcpy() more efficient.

> Looks like there's specific knowledge about the types and instructions
> codes in switches midway through that is not recognizing your new
> pseudos.
>
> One way to find them out is to grep for the instruction codes yours is
> similar to, and then see if you need to add your pseudos

Thanks, I'll try that.

Regards,
Sergey