[LLVMdev] tablegen pattern

[kewuzhang]

On Aug 11, 2014, at 5:32 PM, Matt Arsenault <Matthew.Arsenault at amd.com> wrote:

> On 08/11/2014 02:24 PM, kewuzhang wrote:
>> Hi Guys, 
>> 
>> I have a taget instruction which take a vec4 and returns a vec4.( say instruction  “vec4:$dst mod( vec4:$src)"  )
>> And I want to use it to match i an  ir instruction/intrinsic function( say " float:$dst  llvm.irmod( vec4:$src)"   which takes a vec4, output a float. 
>> 
>> I think the procedure is:  when  I see the intrinsic llvm.irmod, I need to call  "extractlt( mod($src), 0)”, 
>> 
>> So I tried to define a pattern “ def Pat<( i32 ( llvm.irmod vf432:$src)), (extractelt( mod v4f32:$src ), 0)>”,  but it reports ERROR”  Cannot use “extractelt” in an output pattern”.
>> 
>> I knew I can easily do it via lowering operation by separating the “extractelt” node out. But can I do it via tablgen?
> You want the machine equivalent of the extract element, which will probably be something like (EXTRACT_SUBREG (mod $src), sub0)


tks, "machine equivalent” works, 


kevin
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