[LLVMdev] Concerning not relevant argument count in TableGen Patterns.

[Arsen Hakobyan]

Dear all.

I have a problem with the following situation:

I want to handle an intrinsic function in a specific way. The prototype of
my function is:    "/int my_intrinsic_name()/"

So I want to generate a move instruction which should use two register type
operands:   "/mov R1, R2/"

For this purpose I assume that the instruction definition in the
TargetInstrInfo.td file should be like:

at first I am defining the class form my instruction:
*class Mymov<bits<6> op, string instr_asm>:  FI<op, (outs Regs1:$rs),
(ins Regs2:$rt),
     !strconcat(instr_asm, "\t$rt, $rs"), 
     [], NoItinerary> {
     let imm16 = 0;
}*

where *Regs1* and *Regs2* are corresponding *RegisterClasses*. 
Then I need to define the instruction:
*def MOVInstr : Mymov<0x2, "mov">;*
*def : TargetPat<(int_myintrinsicname), (MOVInstr)>;*   /// error: In
anonymous.4: Instruction 'MOVInstr' expects more operands than were
provided./

int the corresponding /inclue/llvm/IR/IntrinsicsTarget.td/ file:

*def int_myintrinsicname : Intrinsic< [llvm_i16_ty], [],
[<IntrinsicProperty>], "llvm.my_intrinsic_name" >;*

This causes an error (shown in a comment) because I have specified an
instruction class which has two operands (one in "outs" list and the other
one in "ins" list, but pattern knows that the SRC has one operand (return
type of the int_myintrinsicname) if i am not mistaken.


So, is there a technique to handle this kind of situation using Tablegen?
Can I use a Pattern when the argument count of SRC and DST does not match to
each other ?

Thanks,
Arsen



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