[LLVMdev] initialize register attributes in instruction definition

[Tom Stellard]

On Fri, Aug 01, 2014 at 01:29:15PM -0700, Matt Arsenault wrote:
> 
> On Aug 1, 2014, at 1:23 PM, kewuzhang <kewu.zhang at amd.com> wrote:
> 
> > 
> > On Jul 31, 2014, at 7:23 PM, Tom Stellard <tom at stellard.net> wrote:
> > 
> >> On Thu, Jul 31, 2014 at 06:41:06PM -0400, kewuzhang wrote:
> >>> Hi All, 
> >>> 
> >>> Is it possible to initialize(set up)  register attributes when we define an instruction?
> >>> 
> >>> like  
> >>> 
> >>> if a register is defined like this:
> >>> 
> >>> " class SC_Register<bits<8> register_num, 
> >>>                   	 REG_FLAG  SC_X,
> >>> 			 REG_FLAG  SC_Y,
> >>> 			 REG_FLAG  SC_Z,
> >>> 			 REG_FLAG  SC_W,
> >>>                  	 string asmstr> : Register<asmstr>
> >>> {
> >>> 	
> >>>    	let HWEncoding{7-0}     = register_num;         // register_num
> >>> 	let HWEncoding{8}     = SC_X;  
> >>> 	let HWEncoding{9}     = SC_Y;  
> >>> …..
> >>> }”
> >>> 
> >>> can I set up the input/ouput register flags like this? or some other way in codegen to make the register flags are set up based on the instructions?
> >>> 
> >>> let Constraints = “$dst.SC_X =1, $src.SC_Y =0" in 
> >> 
> >> This isn't what Constraints are for.  Constraints can be either tied
> >> operands e.g. $dst = $src or @earlyclober $dst, meaning that the $dst
> >> may be written before all source registers are read.
> >> 
> >> Can you explain more about what you are trying to do?  It looks like you
> >> might be trying to force an instruction to uses a specific component of
> >> a vector register.
> >> 
> > 
> > Yes, that is pretty much what i want to do. If I can initialize it in the instruction definition stage( it is operation related).
> > Then I can directly access it for the machine instruction emit.
> > That would be nice.
> > 
> > Tks
> You probably want a register class for each component. Then you can restrict an operand to be a specific component’s register class
> 

Exactly, this is what R600 does.

-Tom