[LLVMdev] where is F7 opcode for TEST instruction on X86?

[Jun Koi]

hi,

at the moment, TEST instruction is defined with 0xf7 opcode, as
demonstrated below.

$ echo "0xf7 0xc0 0x00 0x00 0x00 0x22"|./Release+Asserts/bin/llvm-mc
-disassemble -arch=x86
    .section    __TEXT,__text,regular,pure_instructions
    testl    $570425344, %eax        ## imm = 0x22000000

however, i cannot find anywhere this F7 opcode is defined in
lib/Target/X86/X86InstrArithmetic.td.
we only have TEST defined with F6 & other opcode like below.

any hint please?

thanks.


let isCompare = 1 in {
  let Defs = [EFLAGS] in {
    let isCommutable = 1 in {
      def TEST8rr  : BinOpRR_F<0x84, "test", Xi8 , X86testpat, MRMSrcReg>;
      def TEST16rr : BinOpRR_F<0x84, "test", Xi16, X86testpat, MRMSrcReg>;
      def TEST32rr : BinOpRR_F<0x84, "test", Xi32, X86testpat, MRMSrcReg>;
      def TEST64rr : BinOpRR_F<0x84, "test", Xi64, X86testpat, MRMSrcReg>;
    } // isCommutable

    def TEST8rm    : BinOpRM_F<0x84, "test", Xi8 , X86testpat>;
    def TEST16rm   : BinOpRM_F<0x84, "test", Xi16, X86testpat>;
    def TEST32rm   : BinOpRM_F<0x84, "test", Xi32, X86testpat>;
    def TEST64rm   : BinOpRM_F<0x84, "test", Xi64, X86testpat>;

    def TEST8ri    : BinOpRI_F<0xF6, "test", Xi8 , X86testpat, MRM0r>;
    def TEST16ri   : BinOpRI_F<0xF6, "test", Xi16, X86testpat, MRM0r>;
    def TEST32ri   : BinOpRI_F<0xF6, "test", Xi32, X86testpat, MRM0r>;
    def TEST64ri32 : BinOpRI_F<0xF6, "test", Xi64, X86testpat, MRM0r>;

    def TEST8mi    : BinOpMI_F<"test", Xi8 , X86testpat, MRM0m, 0xF6>;
    def TEST16mi   : BinOpMI_F<"test", Xi16, X86testpat, MRM0m, 0xF6>;
    def TEST32mi   : BinOpMI_F<"test", Xi32, X86testpat, MRM0m, 0xF6>;
    def TEST64mi32 : BinOpMI_F<"test", Xi64, X86testpat, MRM0m, 0xF6>;

    // When testing the result of EXTRACT_SUBREG sub_8bit_hi, make sure the
    // register class is constrained to GR8_NOREX.
    let isPseudo = 1 in
    def TEST8ri_NOREX : I<0, Pseudo, (outs), (ins GR8_NOREX:$src,
i8imm:$mask),
                          "", [], IIC_BIN_NONMEM>, Sched<[WriteALU]>;
  } // Defs = [EFLAGS]

  def TEST8i8    : BinOpAI<0xA8, "test", Xi8 , AL,
                           "{$src, %al|al, $src}">;
  def TEST16i16  : BinOpAI<0xA8, "test", Xi16, AX,
                           "{$src, %ax|ax, $src}">;
  def TEST32i32  : BinOpAI<0xA8, "test", Xi32, EAX,
                           "{$src, %eax|eax, $src}">;
  def TEST64i32  : BinOpAI<0xA8, "test", Xi64, RAX,
                           "{$src, %rax|rax, $src}">;
} // isCompare
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