[LLVMdev] Proposal: AArch64/ARM64 merge from EuroLLVM

[Quentin Colombet]

Hi Jiangning,

On Apr 14, 2014, at 10:31 PM, Jiangning Liu <liujiangning1 at gmail.com> wrote:

> Hi Jim,
> 
> 2014-04-15 4:28 GMT+08:00 Jim Grosbach <grosbach at apple.com>:
> This sounds reasonable. Thanks, all.
> 
> > - CSE of ADRP optimization (Jiangning)
> 
> Quentin may have some input here. He’s done quite a lot of optimizations for ADRP sequences.
> 
> -Jim
> 
> ​Thanks for letting me ​know Quentin may have deep thought around this.
> 
> ​ARM64 generates pseudo instructions ARM64::MOVaddr and friends in ISEL stage, which intends to guarantee address serialization (page address + in-page address), and exposes adrp finally by pass ExpandPseudoInsts. The assumption of ARM64 solution is we don't know the in-page offset can be fused into load/store or not at compile time, and this assumption would turn to be not true any longer for the solution of using global merge as I proposed with the patch.
I think this is orthogonal. If you happen to merge globals they will have the same base address (i.e., the same pseudo instruction) but different offsets.
CSE and such will work like a charm for the pseudos.

Assuming you emit the right instructions at isel time, you will create ADRP, LOADGot, or ADD with symbols. Since you do not know anything on the symbols, CSE will match only the ones that are identical.
You will have a finer granularity to do CSE, but I am not sure it will help that much.
On the other hand, you lose the rematerialization capability, because that feature can only handle one instruction at a time. So you will still be able to rematerialize ADRP but not the LOADGot and ADD with symbols.

> 
> If simply apply the global merge solution to ARM64, probably we should avoid generating pseudo instruction MOVaddr and friends in ISEL stage, but I'm not sure if the LOH solution would still work or not, because,
> 1) ARM64 link-time optimization depends on LOH.
> 2) We don't see linker plug-in in LLVM trunk and it would be hard for me to verify any thoughts.
The LOH solution is also orthogonal. You can see that as a last chance way to optimize those accesses.
That said, if you CSE the ADRP and not the LOADGot, you will indeed create far less candidates for the LOHs because you will have ADRPs with several uses, which is not supported by LOHs.

FYI, the LOH optimization is not a link-time optimization in LLVM, this is really a link-time optimization: on the binary.

> 
> Any concrete suggestion of combining those different ADRP CSE solutions and tests would be appreciated! 
The bottom line is whatever you are doing with merge globals, it is orthogonal with LOHs.
That said I think it is best to keep the pseudo instructions.

Of course I may be wrong and the best way to check would be to measure what happens if you get rid of the pseudo instructions. Do not be too concerned with the impact on the LOHs.

Thanks,
-Quentin

> 
> Thanks,
> -Jiangning
> 
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