[LLVMdev] Missed optimization opportunity with piecewise load shift-or'd together?

[Hal Finkel]

----- Original Message -----
> On Mon, Oct 28, 2013 at 10:09 AM, James Courtier-Dutton
> <james.dutton at gmail.com> wrote:
> > My guess is that this is a missed optimization, but in real life,
> > all
> > projects i have worked fix this in the C or C++ code using macros
> > that
> > change what instructions are used based on target platform and its
> > endedness.
> 
> One reason for writing code like this, i.e. explicitly spelling out
> the accesses to the individual bytes, would be to allow compile-time
> evaluation of the fragment in the D programming language, where
> arbitrarily reinterpreting memory is not supported (although
> integer->integer pointer casts might be supported at some point).
> 
> Would a patch adding the capability to lower this to InstCombine or
> similar have a chance of being accepted, or would that be considered
> to be too rare a spacial case to be worth the added complexity?

I think that a patch for this would be great; I've seen plenty of real-life deserialization code that looks like this.

FWIW, some patterns like this (byte swapping, for example), are matched during CodeGen (see DAGCombiner::visitOR in lib/CodeGen/SelectionDAG/DAGCombiner.cpp), but there is no reason that this pattern cannot be recognized and canonicalized early in the IR (and I think that it should be).

 -Hal

> 
> David
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-- 
Hal Finkel
Assistant Computational Scientist
Leadership Computing Facility
Argonne National Laboratory