[LLVMdev] Post Increment Indirect Move Instructions

[Shashidhar G]

Hi Hal,


     Our Architecture has indirect move instruction which increments the 
pointer implicitly and the target only has i8 type values. So the load 
of i16 will be converted to two i8 target loads wherein after the first 
load instruction, the pointer to the first i8 address will automatically 
increment to point to the next i8 value. So the post increment nature is 
in the Target. A normal i16 indirect load need to be converted to two 
post increment load. SDNodes can be used to define only one value and so 
the Selection DAG cannot to used to encode the information that the 
pointer has been incremented.

I think the description that you mentioned will transform the 
addition/subtraction of a pointer and/from a constant into a pointer and 
an offset(Please correct me if i am wrong). We are doing this 
transformation in the Lowering of the Loads and stores.

Does the Machine Instruction class provides any way to encode this 
information?

Thanks for your help.

Regards,
Shashidhar

On Tuesday 01 October 2013 12:38 AM, Hal Finkel wrote:
> ----- Original Message -----
>> Hi,
>>
>>         We have an architecture where the indirect move instruction
>> implicitly increments the pointer
>> value after the move. We have Instruction format and pattern for this
>> type of instructions.
>>
>> How to encode the information that the pointer is incremented?
> As you seem to be aware, LLVM has patterns specifically to match pre/post increment loads and stores (post_store). In your *ISelLowering.cpp file, you'll need to call setIndexedLoadAction(ISD::POST_INC, <type>, Legal), and the same for setIndexedStoreAction. Then you'll need to implement a getPostIndexedAddressParts function in that same file (you can look in the ARM backend for an example). If you can select your indirect moves using TableGen patterns, then you can probably use the post_store pattern.
>
>   -Hal
>
>> Thanks and regards,
>> Shashidhar
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