[LLVMdev] prevents instruction-scheduler from interfereing instruction pair

[Amara Emerson]

What I meant was to write your own expansion pass and run it after the
scheduler passes, e.g. in the pre-emit stage.
> if (addPreEmitPass())
    printAndVerify("After PreEmit passes")

Though if it's too hacky for you then fair enough.

Amara

On 23 November 2013 03:17, Liu Xin <navy.xliu at gmail.com> wrote:
> Amara,
>
> first, thank you for answering.  but I found expandPsuedo instructions
> actually happens before post-RA, like the following code showing:
> your approach is a little hacky, right? : )
>
> // Expand pseudo instructions before second scheduling pass.
>   addPass(&ExpandPostRAPseudosID);
>   printAndVerify("After ExpandPostRAPseudos");
>
>   // Run pre-sched2 passes.
>   if (addPreSched2())
>     printAndVerify("After PreSched2 passes");
>
>   // Second pass scheduler.
>   if (getOptLevel() != CodeGenOpt::None) {
>     addPass(&PostRASchedulerID);
>     printAndVerify("After PostRAScheduler");
>   }
>
>
> secondly, psuedo instruction is kind of compiler internal representation. I
> wish our instruction pair can disclose to programmer. intrinsics can do
> that.
>
> thanks,
> --lx
>
>
> On Fri, Nov 22, 2013 at 9:45 PM, Amara Emerson <amara.emerson at arm.com>
> wrote:
>>
>> What about describing the instruction pairs as pseudo-instructions, and
>> then expanding them in a machine function pass at the pre-emit stage?
>>
>>
>>
>> Amara
>
>
>
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