[LLVMdev] Modelling M68k registers?

[Owen Anderson]

On Nov 21, 2013, at 5:04 AM, Fredrik Olsson <peylow at gmail.com> wrote:

> This makes me think that maybe subregs is not what I should use, but
> instead treat it as the byte&word load and store in ARM?

The question to ask yourself here is what you want the register allocator to do for you.  The reason for modeling the sub-register relationship is if there is useful bin-packing-like work that you want it to do for you.  If the answer is no, going the route of a single set of register with aliased named is probably simpler.

> Or maybe I should treat data and address registers differently 

You almost certainly want to do this for m68k.  A large aspect of getting good code quality out of it is going to consist of doing a domain-crossing optimization to keep data in address registers when appropriate for its future use.  This is not something LLVM will (currently) give you for free, so you want to design your target description to make it easy for you to do it yourself.

—Owen

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