[LLVMdev] Limit loop vectorizer to SSE

[Frank Winter]

.. forcing the vector size to 4 does not prevent using AVX. I just hit 
the following:

LV: We can vectorize this loop!
LV: Found trip count: 4
LV: The Widest type: 64 bits.
LV: The Widest register is: 256 bits.
LV: Using user VF 4.

Looks like I have to disable AVX somehow. (Which is sad on its own.)

Frank



On 12/11/13 10:34, Renato Golin wrote:
> On 12 November 2013 15:14, Frank Winter <fwinter at jlab.org 
> <mailto:fwinter at jlab.org>> wrote:
>
>     I am asking because the option 'force-vector-width' is too
>     restrictive.
>     I would like to leave open the possibility to use vector width 2.
>
>
> I was about to say that, and you saved us both one cycle. ;)
>
> What you could do is to force an architecture that doesn't have AVX, 
> only SSE. I'm not sure how to do that on the JIT, I suppose setting 
> the Target attributes would be enough. Nor I know what CPU string 
> limits support to SSE, but that should do it.
>
> cheers,
> --renato


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