[LLVMdev] Register coalescer and reg_sequence (virtual super-regs)

[Joe Matarazzo]

The register coalescer treats virtual super register classes -- a
sequential register range composed of multiple hardware registers -- as a
register with sub registers. When making coalescing decisions it thinks
that the virtual super reg interferes with sub reg instances, even though
in reality they shouldn't conflict. That is, they are individual registers
and would be better compared as such for register coalescing decisions
(CoalescerPair::Partial = 0).

For example, I have a super reg that has r20, r21, r22, and r23 physical
registers. This super reg is the dest of a reg_sequence which generates 4
COPY MIs. The first COPY coalesces (merging into r20), but the vregs for
r21-r23 (SUPER_RC:%vreg50:subreg1..subreg3) are never coalesced after that
because doing so generates inteference on %vreg50, the "parent" super reg.

Is there a way to work around this? It causes unnecessary copies.

Thanks,
Joe
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