[LLVMdev] Custom delay slot insertion

[Vikram Singh]

hi 

I am porting llvm 3.1 for a custom processor. I'm taking reference from
sparc architecture. The problem I'm facing that sparc has 1 delay slot in
call and conditional instructions. In my case some have 1 and some have 2
delay slots. But the backend is inserting only 1 delay slot instruction. I
do not know how to insert more than 1 instruction in the delay slots. 
Please suggest some solution. 

vikram



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