[LLVMdev] Predicated Vector Operations

[Arnold Schwaighofer]

On May 10, 2013, at 11:53 AM, dag at cray.com wrote:

> Jeff Bush <jeffbush001 at gmail.com> writes:
> 
>> Ah, I think I get it now.  This was mentioned earlier in the thread,
>> but it didn't click at the time. It sounds like I can do instruction
>> selection with a pattern like (omitting selection of the sources):
>> 
>> let Constraints = "$dst = $oldvalue" in {
>>    def MASKEDARITH : MyInstruction<
>>        (outs VectorReg:$dst),
>>        (ins MaskReg:$mask, VectorReg:$src1, VectorReg:$src2,
>> VectorReg:$oldvalue),
>>        "add $dst {$mask}, $src1, $src2",
>>        [(set v16i32:$dst, (vselect v16i1:$mask, (add v16i32:$src1,
>> v16i32:$src2), v16i32:$oldvalue))]>;
>> }
> 
> Ok, but where does $oldvalue come from?  That is the trickty part as far
> as I can see and is why this isn't quite the same as handling
> two-address instructions.


>From the semantics of your program?

%tx = select %mask, %x, <0.0, 0.0, 0.0 ...>
%ty = select %mask, %y, <0.0, 0.0, 0.0 ...>
%sum = fadd %tx, %ty
%newvalue = select %mask, %sum, %oldvalue << From here?

If you had a designated predicated instruction you would have the same issue. The %oldvalue has to come from somewhere (or be undefined).

%oldval = ... | undef
%newvalue = predicated_fadd %mask, %left, %right, %oldval


I guess, I don’t understand your question.

Instcombine might remove the select %mask, %sum, undef but that is another issue ...