[LLVMdev] Predicated Vector Operations

[Nadav Rotem]

> I'm not sure I understand the full impact of this example, and I would like to.
> 
> What are the desired memory model semantics for a masked store? Specifically, let me suppose a simplified vector model of <2 x i64> on an i64-word-size platform.
> 

Hi Chandler, 

I brought the example in this email thread to show that the optimizations that we currently have won't work on masked load/store operations because they don't take the mask into consideration. The memory model interesting question but I am not sure how it is related. In our example you can see the problem with a single thread. Both MIC and AVX[1] have masked stores operations and they have a different memory model. 

Thanks,
Nadav

[1]  http://software.intel.com/sites/products/documentation/studio/composer/en-us/2011Update/compiler_c/intref_cls/common/intref_avx_maskstore_pd.htm

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