[LLVMdev] Handling Masked Vector Operations

[Chris Lattner]

On May 6, 2013, at 9:35 AM, dag at cray.com wrote:
>>> It's easy enough to write a TableGen pattern to match add+select and
>>> emit a masked instruction.  Alternative, we can always resort to manual
>>> lowering (ugh).
>>> 
>>> For trapping operations this is problematic.  Take a load.  Here's the
>>> same attempt with a load:
>>> 
>>> tt = load [addr]
>>> t1 = select mask, tt, 0
>> 
>> This would not be problematic at the IR level if it was done by branching to
>> one of two basic blocks based on the condition, and doing the load in the
>> appropriate basic block.  Codegen would however need to become powerful enough
>> to turn this construct into your target's predicated load.
> 
> How will that ever happen?  isel has never known much about control flow
> at all.
> 
> Please do NOT remove select until we have a solid replacement in place,
> something that's tested and known to work.
> 
> I cannot object strongly enough.  I've bit my tongue at a few IR
> changes, but not this one.
> 
> Who propsed this change?  Why has it not been discussed on the list?

FWIW, I don't think that removing select has ever been really proposed.  I would also be pretty against such a thing.  

That said, there is a question about how much if conversion should happen on IR vs at the machine level.  There are interesting design problems to be answered there, but AFAIK, no design would remove select entirely.

-Chris
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