[LLVMdev] About the partial update clearence / dependency breaking mechanism

[Silviu Baranga]

Hi Jakob,

Thanks for the reply. I misunderstood the code there, it now
makes sense.

Silviu

> -----Original Message-----
> From: Jakob Stoklund Olesen [mailto:stoklund at 2pi.dk]
> Sent: 25 March 2013 16:43
> To: Silviu Baranga
> Cc: LLVM Developers Mailing List
> Subject: Re: About the partial update clearence / dependency breaking
> mechanism
> 
> 
> On Mar 25, 2013, at 5:02 AM, Silviu Baranga <silbar01 at arm.com> wrote:
> 
> > Hello,
> >
> > I am currently looking into the advantages of using the
> > partial update clearance / dependency breaking mechanism
> > for some ARM cores.
> >
> > It seems that the ARM specific code for this will always
> > return a clearance of 0 for VLD1LNd32 because of the following
> > code in getPartialRegUpdateClearance:
> >
> >> if (UseOp != -1 && MI->getOperand(UseOp).readsReg())
> >>   return 0;
> >
> > so essentially VLD1LNd32 (and potentially other instruction)
> > will never be affected by this. Was this intended or is there
> > a bug here?
> >
> > I'm confused why the dependency breaking code is correct.
> > Why would the dependency breaking mechanism apply only
> > when the register is dead?
> 
> It's breaking *false* dependencies.
> 
> /jakob
> 
>