[LLVMdev] [PATCH] RegScavenger::scavengeRegister

[Jakob Stoklund Olesen]

On Mar 26, 2013, at 10:29 AM, Akira Hatanaka <ahatanak at gmail.com> wrote:

> The size of general purpose integer registers for mips32 is 32-bit and accumulators are 64-bit registers consisting of 32-bit hi/lo register pairs. So you will need two instructions to copy two 32-bit GPR registers to a 64-bit accumulator register. If spilling to multiple registers is unsupported, perhaps I can I define a new register class consisting of paired GPR registers and pseudo copy instructions? 

Yes, that would work. Look at the ARM GPRPair register class.

You don't need pseudo copy instructions, TII::copyPhysReg() is allowed to insert multiple instructions.

> > Also, should RA avoid splitting live intervals of accumulators, which creates copy instructions?
> 
> The alternative to live range splitting is spilling, which is usually worse.
> 
> Here I was assuming register allocator will spill accumulator registers to integer registers instead of directly to stack. In that case, splitting might be worse than spilling since reload requires two GPR-to-accumulator copy instructions while copying one accumulator to another requires four copy instructions (instruction set doesn't have any accumulator-to-accumulator copy instructions):
> 
> copy $vreg_gpr0, $vreg_acc0:lo
> copy $vreg_gpr1, $vreg_acc0:hi
> copy $vreg_acc1:lo, $vreg_gpr0 
> copy $vreg_acc1:hi, $vreg_gpr1

There is no way of preventing copies completely.

Once you create a virtual register with some register class, you must support spilling, reloading, and copying of that register class.

The cross class spilling feature can make these things less frequent, but it can't make them go away completely.

/jakob