[LLVMdev] Types in TableGen instruction selection patterns

[Jakob Stoklund Olesen]

On Mar 25, 2013, at 12:58 PM, Sebastian Pop <spop at codeaurora.org> wrote:

> Sebastian Pop wrote:
>> same mechanism could be useful. It would be nice to be able to write this:
>> 
>>  def insn : Inst<(outs i32:$dst), (ins i32:$src1, i32:$src2),
>>            "some assembler",
>>            [(set $dst, (Op $src1, $src2))]>;
> 
> From the PPC changes, I see that this is already possible under a slightly
> different form:
> 
>   def FSUBS : AForm_2<59, 20,
>                       (outs F4RC:$FRT), (ins F4RC:$FRA, F4RC:$FRB),
>                       "fsubs $FRT, $FRA, $FRB", FPGeneral,
> -                      [(set F4RC:$FRT, (fsub F4RC:$FRA, F4RC:$FRB))]>;
> +                      [(set f32:$FRT, (fsub f32:$FRA, f32:$FRB))]>;

Yes, that is exactly how it should be done.

Thanks, Ulrich!

/jakob