[LLVMdev] Types in TableGen instruction selection patterns

[Jakob Stoklund Olesen]

On Mar 25, 2013, at 12:50 PM, Sebastian Pop <spop at codeaurora.org> wrote:

> Does it make sense to also make this mechanism available in the definition of
> instructions' matching code [], this is the only other place I see where this
> same mechanism could be useful. It would be nice to be able to write this:
> 
>  def insn : Inst<(outs i32:$dst), (ins i32:$src1, i32:$src2),
>            "some assembler",
>            [(set $dst, (Op $src1, $src2))]>;

No, the ins and outs lists must contain register classes. They define the encoding constraints of the instruction operands.

But you should put types in the patterns instead of register classes:

def STFrr   : F3_1<3, 0b100100,
                   (outs), (ins MEMrr:$addr, FPRegs:$src),
                   "st $src, [$addr]",
                   [(store f32:$src, ADDRrr:$addr)]>;

/jakob