[LLVMdev] Simpler types in TableGen isel patterns

[Jakob Stoklund Olesen]

On Mar 21, 2013, at 12:56 PM, Justin Holewinski <justin.holewinski at gmail.com> wrote:

> This sounds great!  I've been bitten in the past by trying to use a single class for multiple types.
> 
> Would it make sense to extend this to all DAG patterns?  If I have an instruction def:
> 
> def ANDN64 : MyInst<(outs Reg64:$d), (ins Reg64:$a, Reg64:$b), "and.64 $d, $a, $b", [(set Reg64:$d, (and (not (Reg64:$a, Reg64:$b))))]>;
> 
> would I now be able to write:
> 
> def ANDN64 : MyInst<(outs Reg64:$d), (ins Reg64:$a, Reg64:$b), "and.64 $d, $a, $b", [(set i64:$d, (and (not (i64:$a, i64:$b))))]>;
> 
> ?

Yes, that was my plan.

The ins and outs lists still need to be register classes for the instruction constraints, but the set pattern doesn't need them.

/jakob