[LLVMdev] Strange spill behaviour

[Jakob Stoklund Olesen]

On Mar 20, 2013, at 2:10 AM, Lee Hammerton <savoury.snax at googlemail.com> wrote:

> Hi,
> 
>  While working some more on the backend, I've added callee register saving and have come across something odd (I assume its because i've not implemented something), this is with optimisations which makes it even more odd :
> 
>       MOV.L   [R7+ 12], R1            ; 4-byte Folded Spill
>       MOV.L   [R7+ 8], R2             ; 4-byte Folded Spill
>       ADD.L   R0,R0 + R1
>       ADD.L   R0,R0 + #7
>       SUB.L   R0,R0 - R2
>       MOV.L   R2, [R7+ 8]             ; 4-byte Folded Reload
>       MOV.L   R1, [R7+ 12]            ; 4-byte Folded Reload
> 
>  I've isolated the epilogue and prologue away from the function (they don't make use of R1 or R2, Calling convention states R0-R3 are used as inputs to a function. R1-R4 are marked as calleesaved. From the above code I cannot see any reason why R1 & R2 are being spilled, I assume the fault lies in my tablegen definitions (relevant ones reproduced below) :

This is not enough information to help you. Try llc -debug-only=regalloc.

/jakob