[LLVMdev] setCC and brcond
Jan Tlatlik
jtlatlik at techfak.uni-bielefeld.de
Tue Mar 19 10:27:51 PDT 2013
Hi there,
I am currently trying to create an LLVM Backend for a RISC architecture
and running into problems with setCC and brcond.
First a few explanations:
The architecture doesn't have a dedicated flag register, but seven
1-bit-wide so called "condition registers", c0-c6,
which can be set by e.g. a compare instruction:
> cmp ne, c0, r1, 123
It also supports conditional execution of _all_ instructions. This,
however, is also the only way to perform a conditional branch:
> c7 cmp ne, c0, r1, 123
> c0 br $destination
Meaning: the branch instruction will be executed, if c0 (set by previous
instruction) holds a non-zero value.
I tried to model this through a special RegisterClass "CondRegs":
def C0 : CReg< 0, "c0">, DwarfRegNum<[32]>;
[...]
def C7 : CReg< 7, "c7">, DwarfRegNum<[39]>;
def CondRegs : RegisterClass<"MXM", [i1], 32,
(add C0, C1, C2, C3, C4, C5, C6,
C7)>; // C7 = constant one
and by expanding SELECT_CC to SETCC and BR_CC to BRcond.
In my IntstrInfo description, I have the following patterns:
//cmp (setcc) instruction
def CMPri : F1<0b0000001101, (outs CondRegs:$cd), (ins GPRegs:$rn,
uimm8:$uimm8),
"c7 cmp\tne, $cd, $rn, $uimm8",
[(set CondRegs:$cd, (setne GPRegs:$rn, uimmZExt8:$uimm8))]>;
//conditional branch
def BRcondrel : F3_1<0b011110,
(outs), (ins CondRegs:$cd, brtarget:$offset),
"$cd br\t$offset",
[(brcond CondRegs:$cd, bb:$offset)]>;
I want to place the setcc result in a condition reg and then do the
conditional branch with the result from the condition reg.
Unfortunately, this doesn't work. The Instruction Selection itself does
work, but in a later pass the compare and branch instructions are deleted:
> DeadMachineInstructionElim: DELETING: BRrel <BB#3>
> DeadMachineInstructionElim: DELETING: BRrel <BB#1>
> DeadMachineInstructionElim: DELETING: BRcondrel %vreg1<kill>, <BB#2>;
CondRegs:%vreg1
> DeadMachineInstructionElim: DELETING: %vreg1<def> = CMPri %vreg0, 0;
CondRegs:%vreg1 GPRegs:%vreg0
What am I missing?
I attached the llc debug output.
Thanks in advance,
Jan Tlatlik
-------------- next part --------------
Args: ./llc if.ll -debug
Features:
CPU:
CGP: Found local addrmode: [Base:%a.addr]
CGP: Found local addrmode: [Base:%a.addr]
CGP: Found local addrmode: [Base:%retval]
CGP: Found local addrmode: [Base:%retval]
CGP: Found local addrmode: [Base:%retval]
Computing probabilities for return
Computing probabilities for if.then
Computing probabilities for if.else
Computing probabilities for entry
set edge entry -> 1 successor weight to 20
set edge entry -> 0 successor weight to 12
=== isZero
Initial selection DAG: BB#0 'isZero:entry'
SelectionDAG has 16 nodes:
0x17d0fb0: ch = EntryToken [ORD=1]
0x17f6880: i32 = FrameIndex<1> [ORD=1]
0x17f6a80: i32 = undef [ORD=1]
0x17d0fb0: <multiple use>
0x17d0fb0: <multiple use>
0x17f6680: i32 = Register %vreg0 [ORD=1]
0x17f6780: i32,ch = CopyFromReg 0x17d0fb0, 0x17f6680 [ORD=1]
0x17f6880: <multiple use>
0x17f6a80: <multiple use>
0x17f6b80: ch = store 0x17d0fb0, 0x17f6780, 0x17f6880, 0x17f6a80<ST4[%a.addr]> [ORD=1]
0x17f6b80: <multiple use>
0x17f6b80: <multiple use>
0x17f6880: <multiple use>
0x17f6a80: <multiple use>
0x17f6c80: i32,ch = load 0x17f6b80, 0x17f6880, 0x17f6a80<LD4[%a.addr]> [ORD=2]
0x17f6980: i32 = Constant<0> [ORD=3]
0x17f6d80: ch = seteq [ORD=3]
0x17f6e80: i1 = setcc 0x17f6c80, 0x17f6980, 0x17f6d80 [ORD=3]
0x17f6f80: i1 = Constant<-1>
0x17f7080: i1 = xor 0x17f6e80, 0x17f6f80
0x17f7180: ch = BasicBlock<if.else 0x17f1f00>
0x17f7280: ch = brcond 0x17f6b80, 0x17f7080, 0x17f7180
0x17f7380: ch = BasicBlock<if.then 0x17f1e58>
0x17f7480: ch = br 0x17f7280, 0x17f7380
Replacing.3 0x17f7080: i1 = xor 0x17f6e80, 0x17f6f80
With: 0x17f8f30: i1 = setcc 0x17f6c80, 0x17f6980, 0x17f8e30
Replacing.1 0x17f6c80: i32,ch = load 0x17f6b80, 0x17f6880, 0x17f6a80<LD4[%a.addr]> [ORD=2]
With: 0x17f6780: i32,ch = CopyFromReg 0x17d0fb0, 0x17f6680 [ORD=1]
and 1 other values
Optimized lowered selection DAG: BB#0 'isZero:entry'
SelectionDAG has 13 nodes:
0x17d0fb0: ch = EntryToken [ORD=1]
0x17d0fb0: <multiple use>
0x17f6680: i32 = Register %vreg0 [ORD=1]
0x17f6780: i32,ch = CopyFromReg 0x17d0fb0, 0x17f6680 [ORD=1]
0x17d0fb0: <multiple use>
0x17f6780: <multiple use>
0x17f6880: i32 = FrameIndex<1> [ORD=1]
0x17f6a80: i32 = undef [ORD=1]
0x17f6b80: ch = store 0x17d0fb0, 0x17f6780, 0x17f6880, 0x17f6a80<ST4[%a.addr]> [ORD=1]
0x17f6780: <multiple use>
0x17f6980: i32 = Constant<0> [ORD=3]
0x17f8e30: ch = setne
0x17f8f30: i1 = setcc 0x17f6780, 0x17f6980, 0x17f8e30
0x17f7180: ch = BasicBlock<if.else 0x17f1f00>
0x17f7280: ch = brcond 0x17f6b80, 0x17f8f30, 0x17f7180
0x17f7380: ch = BasicBlock<if.then 0x17f1e58>
0x17f7480: ch = br 0x17f7280, 0x17f7380
Legally typed node: 0x17f8e30: ch = setne [ID=0]
Legally typed node: 0x17f7380: ch = BasicBlock<if.then 0x17f1e58> [ID=0]
Legally typed node: 0x17f7180: ch = BasicBlock<if.else 0x17f1f00> [ID=0]
Legally typed node: 0x17f6a80: i32 = undef [ORD=1] [ID=0]
Legally typed node: 0x17f6980: i32 = Constant<0> [ORD=3] [ID=0]
Legally typed node: 0x17f6880: i32 = FrameIndex<1> [ORD=1] [ID=0]
Legally typed node: 0x17f6680: i32 = Register %vreg0 [ORD=1] [ID=0]
Legally typed node: 0x17d0fb0: ch = EntryToken [ORD=1] [ID=0]
Legally typed node: 0x17f6780: i32,ch = CopyFromReg 0x17d0fb0, 0x17f6680 [ORD=1] [ID=0]
Legally typed node: 0x17f6b80: ch = store 0x17d0fb0, 0x17f6780, 0x17f6880, 0x17f6a80<ST4[%a.addr]> [ORD=1] [ID=0]
Legally typed node: 0x17f8f30: i1 = setcc 0x17f6780, 0x17f6980, 0x17f8e30 [ID=0]
Legally typed node: 0x17f7280: ch = brcond 0x17f6b80, 0x17f8f30, 0x17f7180 [ID=0]
Legally typed node: 0x17f7480: ch = br 0x17f7280, 0x17f7380 [ID=0]
Legally typed node: 0x7fff9df7bd30: ch = handlenode 0x17f7480 [ID=0]
Type-legalized selection DAG: BB#0 'isZero:entry'
SelectionDAG has 13 nodes:
0x17d0fb0: ch = EntryToken [ORD=1] [ID=-3]
0x17d0fb0: <multiple use>
0x17f6680: i32 = Register %vreg0 [ORD=1] [ID=-3]
0x17f6780: i32,ch = CopyFromReg 0x17d0fb0, 0x17f6680 [ORD=1] [ID=-3]
0x17d0fb0: <multiple use>
0x17f6780: <multiple use>
0x17f6880: i32 = FrameIndex<1> [ORD=1] [ID=-3]
0x17f6a80: i32 = undef [ORD=1] [ID=-3]
0x17f6b80: ch = store 0x17d0fb0, 0x17f6780, 0x17f6880, 0x17f6a80<ST4[%a.addr]> [ORD=1] [ID=-3]
0x17f6780: <multiple use>
0x17f6980: i32 = Constant<0> [ORD=3] [ID=-3]
0x17f8e30: ch = setne [ID=-3]
0x17f8f30: i1 = setcc 0x17f6780, 0x17f6980, 0x17f8e30 [ID=-3]
0x17f7180: ch = BasicBlock<if.else 0x17f1f00> [ID=-3]
0x17f7280: ch = brcond 0x17f6b80, 0x17f8f30, 0x17f7180 [ID=-3]
0x17f7380: ch = BasicBlock<if.then 0x17f1e58> [ID=-3]
0x17f7480: ch = br 0x17f7280, 0x17f7380 [ID=-3]
Legalized selection DAG: BB#0 'isZero:entry'
SelectionDAG has 13 nodes:
0x17d0fb0: ch = EntryToken [ORD=1] [ID=0]
0x17d0fb0: <multiple use>
0x17f6680: i32 = Register %vreg0 [ORD=1] [ID=1]
0x17f6780: i32,ch = CopyFromReg 0x17d0fb0, 0x17f6680 [ORD=1] [ID=8]
0x17d0fb0: <multiple use>
0x17f6780: <multiple use>
0x17f6880: i32 = FrameIndex<1> [ORD=1] [ID=2]
0x17f6a80: i32 = undef [ORD=1] [ID=4]
0x17f6b80: ch = store 0x17d0fb0, 0x17f6780, 0x17f6880, 0x17f6a80<ST4[%a.addr]> [ORD=1] [ID=10]
0x17f6780: <multiple use>
0x17f6980: i32 = Constant<0> [ORD=3] [ID=3]
0x17f8e30: ch = setne [ID=7]
0x17f8f30: i1 = setcc 0x17f6780, 0x17f6980, 0x17f8e30 [ID=9]
0x17f7180: ch = BasicBlock<if.else 0x17f1f00> [ID=5]
0x17f7280: ch = brcond 0x17f6b80, 0x17f8f30, 0x17f7180 [ID=11]
0x17f7380: ch = BasicBlock<if.then 0x17f1e58> [ID=6]
0x17f7480: ch = br 0x17f7280, 0x17f7380 [ID=12]
Optimized legalized selection DAG: BB#0 'isZero:entry'
SelectionDAG has 13 nodes:
0x17d0fb0: ch = EntryToken [ORD=1] [ID=0]
0x17d0fb0: <multiple use>
0x17f6680: i32 = Register %vreg0 [ORD=1] [ID=1]
0x17f6780: i32,ch = CopyFromReg 0x17d0fb0, 0x17f6680 [ORD=1] [ID=8]
0x17d0fb0: <multiple use>
0x17f6780: <multiple use>
0x17f6880: i32 = FrameIndex<1> [ORD=1] [ID=2]
0x17f6a80: i32 = undef [ORD=1] [ID=4]
0x17f6b80: ch = store 0x17d0fb0, 0x17f6780, 0x17f6880, 0x17f6a80<ST4[%a.addr]> [ORD=1] [ID=10]
0x17f6780: <multiple use>
0x17f6980: i32 = Constant<0> [ORD=3] [ID=3]
0x17f8e30: ch = setne [ID=7]
0x17f8f30: i1 = setcc 0x17f6780, 0x17f6980, 0x17f8e30 [ID=9]
0x17f7180: ch = BasicBlock<if.else 0x17f1f00> [ID=5]
0x17f7280: ch = brcond 0x17f6b80, 0x17f8f30, 0x17f7180 [ID=11]
0x17f7380: ch = BasicBlock<if.then 0x17f1e58> [ID=6]
0x17f7480: ch = br 0x17f7280, 0x17f7380 [ID=12]
===== Instruction selection begins: BB#0 'entry'
ISEL: Starting pattern match on root node: 0x17f7480: ch = br 0x17f7280, 0x17f7380 [ID=12]
Skipped scope entry (due to false predicate) at index 2, continuing at 59
Skipped scope entry (due to false predicate) at index 61, continuing at 219
Skipped scope entry (due to false predicate) at index 220, continuing at 261
Skipped scope entry (due to false predicate) at index 262, continuing at 303
Skipped scope entry (due to false predicate) at index 304, continuing at 345
Skipped scope entry (due to false predicate) at index 346, continuing at 387
Skipped scope entry (due to false predicate) at index 388, continuing at 429
Skipped scope entry (due to false predicate) at index 430, continuing at 471
Skipped scope entry (due to false predicate) at index 472, continuing at 513
Skipped scope entry (due to false predicate) at index 514, continuing at 559
Skipped scope entry (due to false predicate) at index 560, continuing at 605
Skipped scope entry (due to false predicate) at index 606, continuing at 651
Skipped scope entry (due to false predicate) at index 652, continuing at 685
Skipped scope entry (due to false predicate) at index 686, continuing at 718
Skipped scope entry (due to false predicate) at index 719, continuing at 730
Skipped scope entry (due to false predicate) at index 731, continuing at 767
Morphed node: 0x17f7480: ch = BRrel 0x17f7380, 0x17f7280
ISEL: Match complete!
ISEL: Starting pattern match on root node: 0x17f7280: ch = brcond 0x17f6b80, 0x17f8f30, 0x17f7180 [ID=11]
Skipped scope entry (due to false predicate) at index 2, continuing at 59
Skipped scope entry (due to false predicate) at index 61, continuing at 219
Skipped scope entry (due to false predicate) at index 220, continuing at 261
Skipped scope entry (due to false predicate) at index 262, continuing at 303
Skipped scope entry (due to false predicate) at index 304, continuing at 345
Skipped scope entry (due to false predicate) at index 346, continuing at 387
Skipped scope entry (due to false predicate) at index 388, continuing at 429
Skipped scope entry (due to false predicate) at index 430, continuing at 471
Skipped scope entry (due to false predicate) at index 472, continuing at 513
Skipped scope entry (due to false predicate) at index 514, continuing at 559
Skipped scope entry (due to false predicate) at index 560, continuing at 605
Skipped scope entry (due to false predicate) at index 606, continuing at 651
Skipped scope entry (due to false predicate) at index 652, continuing at 685
Skipped scope entry (due to false predicate) at index 686, continuing at 718
Skipped scope entry (due to false predicate) at index 719, continuing at 730
Skipped scope entry (due to false predicate) at index 731, continuing at 767
Skipped scope entry (due to false predicate) at index 768, continuing at 787
Morphed node: 0x17f7280: ch = BRcondrel 0x17f8f30, 0x17f7180, 0x17f6b80
ISEL: Match complete!
ISEL: Starting pattern match on root node: 0x17f6b80: ch = store 0x17d0fb0, 0x17f6780, 0x17f6880, 0x17f6a80<ST4[%a.addr]> [ORD=1] [ID=10]
Skipped scope entry (due to false predicate) at index 2, continuing at 59
Morphed node: 0x17f6b80: ch = STWi13 0x17f6c80, 0x17f6d80, 0x17f6780, 0x17d0fb0<Mem:ST4[%a.addr]> [ORD=1]
ISEL: Match complete!
ISEL: Starting pattern match on root node: 0x17f8f30: i1 = setcc 0x17f6780, 0x17f6980, 0x17f8e30 [ID=9]
Skipped scope entry (due to false predicate) at index 2, continuing at 59
Skipped scope entry (due to false predicate) at index 61, continuing at 219
Skipped scope entry (due to false predicate) at index 220, continuing at 261
Skipped scope entry (due to false predicate) at index 262, continuing at 303
Skipped scope entry (due to false predicate) at index 304, continuing at 345
Skipped scope entry (due to false predicate) at index 346, continuing at 387
Skipped scope entry (due to false predicate) at index 388, continuing at 429
Skipped scope entry (due to false predicate) at index 430, continuing at 471
Skipped scope entry (due to false predicate) at index 472, continuing at 513
Skipped scope entry (due to false predicate) at index 514, continuing at 559
Skipped scope entry (due to false predicate) at index 560, continuing at 605
Skipped scope entry (due to false predicate) at index 606, continuing at 651
Morphed node: 0x17f8f30: i1 = CMPri 0x17f6780, 0x17f6d80
ISEL: Match complete!
===== Instruction selection ends:
Selected selection DAG: BB#0 'isZero:entry'
SelectionDAG has 11 nodes:
0x17d0fb0: ch = EntryToken [ORD=1]
0x17d0fb0: <multiple use>
0x17f6680: i32 = Register %vreg0 [ORD=1]
0x17f6780: i32,ch = CopyFromReg 0x17d0fb0, 0x17f6680 [ORD=1]
0x17f6d80: i32 = TargetConstant<0>
0x17f7380: ch = BasicBlock<if.then 0x17f1e58>
0x17f6780: <multiple use>
0x17f6d80: <multiple use>
0x17f8f30: i1 = CMPri 0x17f6780, 0x17f6d80
0x17f7180: ch = BasicBlock<if.else 0x17f1f00>
0x17f6c80: i32 = TargetFrameIndex<1>
0x17f6d80: <multiple use>
0x17f6780: <multiple use>
0x17d0fb0: <multiple use>
0x17f6b80: ch = STWi13 0x17f6c80, 0x17f6d80, 0x17f6780, 0x17d0fb0<Mem:ST4[%a.addr]> [ORD=1]
0x17f7280: ch = BRcondrel 0x17f8f30, 0x17f7180, 0x17f6b80
0x17f7480: ch = BRrel 0x17f7380, 0x17f7280
********** List Scheduling BB#0 'entry' **********
SU(0): 0x17f7480: ch = BRrel 0x17f7380, 0x17f7280 [ID=0]
# preds left : 1
# succs left : 0
# rdefs left : 0
Latency : 1
Depth : 0
Height : 0
Predecessors:
ch SU(1): Latency=1
SU(1): 0x17f7280: ch = BRcondrel 0x17f8f30, 0x17f7180, 0x17f6b80 [ID=1]
# preds left : 2
# succs left : 1
# rdefs left : 0
Latency : 1
Depth : 0
Height : 0
Predecessors:
val SU(4): Latency=1
ch SU(2): Latency=1
Successors:
ch SU(0): Latency=1
SU(2): 0x17f6b80: ch = STWi13 0x17f6c80, 0x17f6d80, 0x17f6780, 0x17d0fb0<Mem:ST4[%a.addr]> [ORD=1] [ID=2]
# preds left : 1
# succs left : 1
# rdefs left : 0
Latency : 1
Depth : 0
Height : 0
Predecessors:
val SU(3): Latency=1
Successors:
ch SU(1): Latency=1
SU(3): 0x17f6780: i32,ch = CopyFromReg 0x17d0fb0, 0x17f6680 [ORD=1] [ID=3]
# preds left : 0
# succs left : 2
# rdefs left : 1
Latency : 1
Depth : 0
Height : 0
Successors:
val SU(2): Latency=1
val SU(4): Latency=1
SU(4): 0x17f8f30: i1 = CMPri 0x17f6780, 0x17f6d80 [ID=4]
# preds left : 1
# succs left : 1
# rdefs left : 1
Latency : 1
Depth : 0
Height : 0
Predecessors:
val SU(3): Latency=1
Successors:
val SU(1): Latency=1
Examining Available:
Height 0: SU(0): 0x17f7480: ch = BRrel 0x17f7380, 0x17f7280 [ID=0]
*** Scheduling [0]: SU(0): 0x17f7480: ch = BRrel 0x17f7380, 0x17f7280 [ID=0]
Examining Available:
Height 1: SU(1): 0x17f7280: ch = BRcondrel 0x17f8f30, 0x17f7180, 0x17f6b80 [ID=1]
*** Scheduling [1]: SU(1): 0x17f7280: ch = BRcondrel 0x17f8f30, 0x17f7180, 0x17f6b80 [ID=1]
CondRegs: 1 / 0
Examining Available:
RegPressureDiff SU(4): 0 != SU(2): 1
Height 2: SU(4): 0x17f8f30: i1 = CMPri 0x17f6780, 0x17f6d80 [ID=4]
Height 2: SU(2): 0x17f6b80: ch = STWi13 0x17f6c80, 0x17f6d80, 0x17f6780, 0x17d0fb0<Mem:ST4[%a.addr]> [ORD=1] [ID=2]
RegPressureDiff SU(4): 0 != SU(2): 1
*** Scheduling [2]: SU(4): 0x17f8f30: i1 = CMPri 0x17f6780, 0x17f6d80 [ID=4]
GPRegs: 1 / 0
Examining Available:
Height 2: SU(2): 0x17f6b80: ch = STWi13 0x17f6c80, 0x17f6d80, 0x17f6780, 0x17d0fb0<Mem:ST4[%a.addr]> [ORD=1] [ID=2]
*** Scheduling [3]: SU(2): 0x17f6b80: ch = STWi13 0x17f6c80, 0x17f6d80, 0x17f6780, 0x17d0fb0<Mem:ST4[%a.addr]> [ORD=1] [ID=2]
GPRegs: 1 / 0
Examining Available:
Height 4: SU(3): 0x17f6780: i32,ch = CopyFromReg 0x17d0fb0, 0x17f6680 [ORD=1] [ID=3]
*** Scheduling [4]: SU(3): 0x17f6780: i32,ch = CopyFromReg 0x17d0fb0, 0x17f6680 [ORD=1] [ID=3]
*** Final schedule ***
SU(3): 0x17f6780: i32,ch = CopyFromReg 0x17d0fb0, 0x17f6680 [ORD=1] [ID=3]
SU(2): 0x17f6b80: ch = STWi13 0x17f6c80, 0x17f6d80, 0x17f6780, 0x17d0fb0<Mem:ST4[%a.addr]> [ORD=1] [ID=2]
SU(4): 0x17f8f30: i1 = CMPri 0x17f6780, 0x17f6d80 [ID=4]
SU(1): 0x17f7280: ch = BRcondrel 0x17f8f30, 0x17f7180, 0x17f6b80 [ID=1]
SU(0): 0x17f7480: ch = BRrel 0x17f7380, 0x17f7280 [ID=0]
Total amount of phi nodes to update: 0
Initial selection DAG: BB#2 'isZero:if.else'
SelectionDAG has 5 nodes:
0x17d0fb0: ch = EntryToken [ORD=4]
0x17f6d80: i32 = Constant<0> [ORD=4]
0x17f6c80: i32 = FrameIndex<0> [ORD=4]
0x17f7480: i32 = undef [ORD=4]
0x17f7280: ch = store 0x17d0fb0, 0x17f6d80, 0x17f6c80, 0x17f7480<ST4[%retval]> [ORD=4]
Optimized lowered selection DAG: BB#2 'isZero:if.else'
SelectionDAG has 5 nodes:
0x17d0fb0: ch = EntryToken [ORD=4]
0x17f6d80: i32 = Constant<0> [ORD=4]
0x17f6c80: i32 = FrameIndex<0> [ORD=4]
0x17f7480: i32 = undef [ORD=4]
0x17f7280: ch = store 0x17d0fb0, 0x17f6d80, 0x17f6c80, 0x17f7480<ST4[%retval]> [ORD=4]
Legally typed node: 0x17f7480: i32 = undef [ORD=4] [ID=0]
Legally typed node: 0x17f6c80: i32 = FrameIndex<0> [ORD=4] [ID=0]
Legally typed node: 0x17f6d80: i32 = Constant<0> [ORD=4] [ID=0]
Legally typed node: 0x17d0fb0: ch = EntryToken [ORD=4] [ID=0]
Legally typed node: 0x17f7280: ch = store 0x17d0fb0, 0x17f6d80, 0x17f6c80, 0x17f7480<ST4[%retval]> [ORD=4] [ID=0]
Legally typed node: 0x7fff9df7bd30: ch = handlenode 0x17f7280 [ID=0]
Type-legalized selection DAG: BB#2 'isZero:if.else'
SelectionDAG has 5 nodes:
0x17d0fb0: ch = EntryToken [ORD=4] [ID=-3]
0x17f6d80: i32 = Constant<0> [ORD=4] [ID=-3]
0x17f6c80: i32 = FrameIndex<0> [ORD=4] [ID=-3]
0x17f7480: i32 = undef [ORD=4] [ID=-3]
0x17f7280: ch = store 0x17d0fb0, 0x17f6d80, 0x17f6c80, 0x17f7480<ST4[%retval]> [ORD=4] [ID=-3]
Legalized selection DAG: BB#2 'isZero:if.else'
SelectionDAG has 5 nodes:
0x17d0fb0: ch = EntryToken [ORD=4] [ID=0]
0x17f6d80: i32 = Constant<0> [ORD=4] [ID=1]
0x17f6c80: i32 = FrameIndex<0> [ORD=4] [ID=2]
0x17f7480: i32 = undef [ORD=4] [ID=3]
0x17f7280: ch = store 0x17d0fb0, 0x17f6d80, 0x17f6c80, 0x17f7480<ST4[%retval]> [ORD=4] [ID=4]
Optimized legalized selection DAG: BB#2 'isZero:if.else'
SelectionDAG has 5 nodes:
0x17d0fb0: ch = EntryToken [ORD=4] [ID=0]
0x17f6d80: i32 = Constant<0> [ORD=4] [ID=1]
0x17f6c80: i32 = FrameIndex<0> [ORD=4] [ID=2]
0x17f7480: i32 = undef [ORD=4] [ID=3]
0x17f7280: ch = store 0x17d0fb0, 0x17f6d80, 0x17f6c80, 0x17f7480<ST4[%retval]> [ORD=4] [ID=4]
===== Instruction selection begins: BB#2 'if.else'
ISEL: Starting pattern match on root node: 0x17f7280: ch = store 0x17d0fb0, 0x17f6d80, 0x17f6c80, 0x17f7480<ST4[%retval]> [ORD=4] [ID=4]
Skipped scope entry (due to false predicate) at index 2, continuing at 59
Morphed node: 0x17f7280: ch = STWi13 0x17f6b80, 0x17f8f30, 0x17f6d80, 0x17d0fb0<Mem:ST4[%retval]> [ORD=4]
ISEL: Match complete!
ISEL: Starting pattern match on root node: 0x17f6d80: i32 = Constant<0> [ORD=4] [ID=1]
Skipped scope entry (due to false predicate) at index 2, continuing at 59
Skipped scope entry (due to false predicate) at index 61, continuing at 219
Skipped scope entry (due to false predicate) at index 220, continuing at 261
Skipped scope entry (due to false predicate) at index 262, continuing at 303
Skipped scope entry (due to false predicate) at index 304, continuing at 345
Skipped scope entry (due to false predicate) at index 346, continuing at 387
Skipped scope entry (due to false predicate) at index 388, continuing at 429
Skipped scope entry (due to false predicate) at index 430, continuing at 471
Skipped scope entry (due to false predicate) at index 472, continuing at 513
Skipped scope entry (due to false predicate) at index 514, continuing at 559
Skipped scope entry (due to false predicate) at index 560, continuing at 605
Skipped scope entry (due to false predicate) at index 606, continuing at 651
Skipped scope entry (due to false predicate) at index 652, continuing at 685
Morphed node: 0x17f6d80: i32 = MOVri 0x17f8f30 [ORD=4]
ISEL: Match complete!
===== Instruction selection ends:
Selected selection DAG: BB#2 'isZero:if.else'
SelectionDAG has 5 nodes:
0x17f8f30: i32 = TargetConstant<0>
0x17f6b80: i32 = TargetFrameIndex<0>
0x17f8f30: <multiple use>
0x17f8f30: <multiple use>
0x17f6d80: i32 = MOVri 0x17f8f30 [ORD=4]
0x17d0fb0: ch = EntryToken [ORD=4]
0x17f7280: ch = STWi13 0x17f6b80, 0x17f8f30, 0x17f6d80, 0x17d0fb0<Mem:ST4[%retval]> [ORD=4]
********** List Scheduling BB#2 'if.else' **********
SU(0): 0x17f7280: ch = STWi13 0x17f6b80, 0x17f8f30, 0x17f6d80, 0x17d0fb0<Mem:ST4[%retval]> [ORD=4] [ID=0]
# preds left : 1
# succs left : 0
# rdefs left : 0
Latency : 1
Depth : 0
Height : 0
Predecessors:
val SU(1): Latency=1
SU(1): 0x17f6d80: i32 = MOVri 0x17f8f30 [ORD=4] [ID=1]
# preds left : 0
# succs left : 1
# rdefs left : 1
Latency : 1
Depth : 0
Height : 0
Successors:
val SU(0): Latency=1
Examining Available:
Height 0: SU(0): 0x17f7280: ch = STWi13 0x17f6b80, 0x17f8f30, 0x17f6d80, 0x17d0fb0<Mem:ST4[%retval]> [ORD=4] [ID=0]
*** Scheduling [0]: SU(0): 0x17f7280: ch = STWi13 0x17f6b80, 0x17f8f30, 0x17f6d80, 0x17d0fb0<Mem:ST4[%retval]> [ORD=4] [ID=0]
GPRegs: 1 / 0
Examining Available:
Height 1: SU(1): 0x17f6d80: i32 = MOVri 0x17f8f30 [ORD=4] [ID=1]
*** Scheduling [1]: SU(1): 0x17f6d80: i32 = MOVri 0x17f8f30 [ORD=4] [ID=1]
*** Final schedule ***
SU(1): 0x17f6d80: i32 = MOVri 0x17f8f30 [ORD=4] [ID=1]
SU(0): 0x17f7280: ch = STWi13 0x17f6b80, 0x17f8f30, 0x17f6d80, 0x17d0fb0<Mem:ST4[%retval]> [ORD=4] [ID=0]
Total amount of phi nodes to update: 0
Initial selection DAG: BB#1 'isZero:if.then'
SelectionDAG has 8 nodes:
0x17f7280: i32 = Constant<0>
0x17d0fb0: ch = EntryToken [ORD=5]
0x17f8f30: i32 = Constant<1> [ORD=5]
0x17f6b80: i32 = FrameIndex<0> [ORD=5]
0x17f6d80: i32 = undef [ORD=5]
0x17f6c80: ch = store 0x17d0fb0, 0x17f8f30, 0x17f6b80, 0x17f6d80<ST4[%retval]> [ORD=5]
0x17f7480: ch = BasicBlock<return 0x17f1fa8>
0x17f6780: ch = br 0x17f6c80, 0x17f7480
Optimized lowered selection DAG: BB#1 'isZero:if.then'
SelectionDAG has 7 nodes:
0x17d0fb0: ch = EntryToken [ORD=5]
0x17f8f30: i32 = Constant<1> [ORD=5]
0x17f6b80: i32 = FrameIndex<0> [ORD=5]
0x17f6d80: i32 = undef [ORD=5]
0x17f6c80: ch = store 0x17d0fb0, 0x17f8f30, 0x17f6b80, 0x17f6d80<ST4[%retval]> [ORD=5]
0x17f7480: ch = BasicBlock<return 0x17f1fa8>
0x17f6780: ch = br 0x17f6c80, 0x17f7480
Legally typed node: 0x17f7480: ch = BasicBlock<return 0x17f1fa8> [ID=0]
Legally typed node: 0x17f6d80: i32 = undef [ORD=5] [ID=0]
Legally typed node: 0x17f6b80: i32 = FrameIndex<0> [ORD=5] [ID=0]
Legally typed node: 0x17f8f30: i32 = Constant<1> [ORD=5] [ID=0]
Legally typed node: 0x17d0fb0: ch = EntryToken [ORD=5] [ID=0]
Legally typed node: 0x17f6c80: ch = store 0x17d0fb0, 0x17f8f30, 0x17f6b80, 0x17f6d80<ST4[%retval]> [ORD=5] [ID=0]
Legally typed node: 0x17f6780: ch = br 0x17f6c80, 0x17f7480 [ID=0]
Legally typed node: 0x7fff9df7bd30: ch = handlenode 0x17f6780 [ID=0]
Type-legalized selection DAG: BB#1 'isZero:if.then'
SelectionDAG has 7 nodes:
0x17d0fb0: ch = EntryToken [ORD=5] [ID=-3]
0x17f8f30: i32 = Constant<1> [ORD=5] [ID=-3]
0x17f6b80: i32 = FrameIndex<0> [ORD=5] [ID=-3]
0x17f6d80: i32 = undef [ORD=5] [ID=-3]
0x17f6c80: ch = store 0x17d0fb0, 0x17f8f30, 0x17f6b80, 0x17f6d80<ST4[%retval]> [ORD=5] [ID=-3]
0x17f7480: ch = BasicBlock<return 0x17f1fa8> [ID=-3]
0x17f6780: ch = br 0x17f6c80, 0x17f7480 [ID=-3]
Legalized selection DAG: BB#1 'isZero:if.then'
SelectionDAG has 7 nodes:
0x17d0fb0: ch = EntryToken [ORD=5] [ID=0]
0x17f8f30: i32 = Constant<1> [ORD=5] [ID=1]
0x17f6b80: i32 = FrameIndex<0> [ORD=5] [ID=2]
0x17f6d80: i32 = undef [ORD=5] [ID=3]
0x17f6c80: ch = store 0x17d0fb0, 0x17f8f30, 0x17f6b80, 0x17f6d80<ST4[%retval]> [ORD=5] [ID=5]
0x17f7480: ch = BasicBlock<return 0x17f1fa8> [ID=4]
0x17f6780: ch = br 0x17f6c80, 0x17f7480 [ID=6]
Optimized legalized selection DAG: BB#1 'isZero:if.then'
SelectionDAG has 7 nodes:
0x17d0fb0: ch = EntryToken [ORD=5] [ID=0]
0x17f8f30: i32 = Constant<1> [ORD=5] [ID=1]
0x17f6b80: i32 = FrameIndex<0> [ORD=5] [ID=2]
0x17f6d80: i32 = undef [ORD=5] [ID=3]
0x17f6c80: ch = store 0x17d0fb0, 0x17f8f30, 0x17f6b80, 0x17f6d80<ST4[%retval]> [ORD=5] [ID=5]
0x17f7480: ch = BasicBlock<return 0x17f1fa8> [ID=4]
0x17f6780: ch = br 0x17f6c80, 0x17f7480 [ID=6]
===== Instruction selection begins: BB#1 'if.then'
ISEL: Starting pattern match on root node: 0x17f6780: ch = br 0x17f6c80, 0x17f7480 [ID=6]
Skipped scope entry (due to false predicate) at index 2, continuing at 59
Skipped scope entry (due to false predicate) at index 61, continuing at 219
Skipped scope entry (due to false predicate) at index 220, continuing at 261
Skipped scope entry (due to false predicate) at index 262, continuing at 303
Skipped scope entry (due to false predicate) at index 304, continuing at 345
Skipped scope entry (due to false predicate) at index 346, continuing at 387
Skipped scope entry (due to false predicate) at index 388, continuing at 429
Skipped scope entry (due to false predicate) at index 430, continuing at 471
Skipped scope entry (due to false predicate) at index 472, continuing at 513
Skipped scope entry (due to false predicate) at index 514, continuing at 559
Skipped scope entry (due to false predicate) at index 560, continuing at 605
Skipped scope entry (due to false predicate) at index 606, continuing at 651
Skipped scope entry (due to false predicate) at index 652, continuing at 685
Skipped scope entry (due to false predicate) at index 686, continuing at 718
Skipped scope entry (due to false predicate) at index 719, continuing at 730
Skipped scope entry (due to false predicate) at index 731, continuing at 767
Morphed node: 0x17f6780: ch = BRrel 0x17f7480, 0x17f6c80
ISEL: Match complete!
ISEL: Starting pattern match on root node: 0x17f6c80: ch = store 0x17d0fb0, 0x17f8f30, 0x17f6b80, 0x17f6d80<ST4[%retval]> [ORD=5] [ID=5]
Skipped scope entry (due to false predicate) at index 2, continuing at 59
Morphed node: 0x17f6c80: ch = STWi13 0x17f7280, 0x17f7380, 0x17f8f30, 0x17d0fb0<Mem:ST4[%retval]> [ORD=5]
ISEL: Match complete!
ISEL: Starting pattern match on root node: 0x17f8f30: i32 = Constant<1> [ORD=5] [ID=1]
Skipped scope entry (due to false predicate) at index 2, continuing at 59
Skipped scope entry (due to false predicate) at index 61, continuing at 219
Skipped scope entry (due to false predicate) at index 220, continuing at 261
Skipped scope entry (due to false predicate) at index 262, continuing at 303
Skipped scope entry (due to false predicate) at index 304, continuing at 345
Skipped scope entry (due to false predicate) at index 346, continuing at 387
Skipped scope entry (due to false predicate) at index 388, continuing at 429
Skipped scope entry (due to false predicate) at index 430, continuing at 471
Skipped scope entry (due to false predicate) at index 472, continuing at 513
Skipped scope entry (due to false predicate) at index 514, continuing at 559
Skipped scope entry (due to false predicate) at index 560, continuing at 605
Skipped scope entry (due to false predicate) at index 606, continuing at 651
Skipped scope entry (due to false predicate) at index 652, continuing at 685
Morphed node: 0x17f8f30: i32 = MOVri 0x17f6b80 [ORD=5]
ISEL: Match complete!
===== Instruction selection ends:
Selected selection DAG: BB#1 'isZero:if.then'
SelectionDAG has 8 nodes:
0x17f7480: ch = BasicBlock<return 0x17f1fa8>
0x17f7280: i32 = TargetFrameIndex<0>
0x17f7380: i32 = TargetConstant<0>
0x17f6b80: i32 = TargetConstant<1>
0x17f8f30: i32 = MOVri 0x17f6b80 [ORD=5]
0x17d0fb0: ch = EntryToken [ORD=5]
0x17f6c80: ch = STWi13 0x17f7280, 0x17f7380, 0x17f8f30, 0x17d0fb0<Mem:ST4[%retval]> [ORD=5]
0x17f6780: ch = BRrel 0x17f7480, 0x17f6c80
********** List Scheduling BB#1 'if.then' **********
SU(0): 0x17f6780: ch = BRrel 0x17f7480, 0x17f6c80 [ID=0]
# preds left : 1
# succs left : 0
# rdefs left : 0
Latency : 1
Depth : 0
Height : 0
Predecessors:
ch SU(1): Latency=1
SU(1): 0x17f6c80: ch = STWi13 0x17f7280, 0x17f7380, 0x17f8f30, 0x17d0fb0<Mem:ST4[%retval]> [ORD=5] [ID=1]
# preds left : 1
# succs left : 1
# rdefs left : 0
Latency : 1
Depth : 0
Height : 0
Predecessors:
val SU(2): Latency=1
Successors:
ch SU(0): Latency=1
SU(2): 0x17f8f30: i32 = MOVri 0x17f6b80 [ORD=5] [ID=2]
# preds left : 0
# succs left : 1
# rdefs left : 1
Latency : 1
Depth : 0
Height : 0
Successors:
val SU(1): Latency=1
Examining Available:
Height 0: SU(0): 0x17f6780: ch = BRrel 0x17f7480, 0x17f6c80 [ID=0]
*** Scheduling [0]: SU(0): 0x17f6780: ch = BRrel 0x17f7480, 0x17f6c80 [ID=0]
Examining Available:
Height 1: SU(1): 0x17f6c80: ch = STWi13 0x17f7280, 0x17f7380, 0x17f8f30, 0x17d0fb0<Mem:ST4[%retval]> [ORD=5] [ID=1]
*** Scheduling [1]: SU(1): 0x17f6c80: ch = STWi13 0x17f7280, 0x17f7380, 0x17f8f30, 0x17d0fb0<Mem:ST4[%retval]> [ORD=5] [ID=1]
GPRegs: 1 / 0
Examining Available:
Height 2: SU(2): 0x17f8f30: i32 = MOVri 0x17f6b80 [ORD=5] [ID=2]
*** Scheduling [2]: SU(2): 0x17f8f30: i32 = MOVri 0x17f6b80 [ORD=5] [ID=2]
*** Final schedule ***
SU(2): 0x17f8f30: i32 = MOVri 0x17f6b80 [ORD=5] [ID=2]
SU(1): 0x17f6c80: ch = STWi13 0x17f7280, 0x17f7380, 0x17f8f30, 0x17d0fb0<Mem:ST4[%retval]> [ORD=5] [ID=1]
SU(0): 0x17f6780: ch = BRrel 0x17f7480, 0x17f6c80 [ID=0]
Total amount of phi nodes to update: 0
Initial selection DAG: BB#3 'isZero:return'
SelectionDAG has 8 nodes:
0x17d0fb0: ch = EntryToken [ORD=6]
0x17f7380: i32 = Constant<0>
0x17d0fb0: <multiple use>
0x17f6c80: i32 = Register %R2
0x17d0fb0: <multiple use>
0x17f6b80: i32 = FrameIndex<0> [ORD=6]
0x17f7280: i32 = undef [ORD=6]
0x17f6780: i32,ch = load 0x17d0fb0, 0x17f6b80, 0x17f7280<LD4[%retval]> [ORD=6]
0x17f7480: ch,glue = CopyToReg 0x17d0fb0, 0x17f6c80, 0x17f6780
0x17f7480: <multiple use>
0x17f7480: <multiple use>
0x17f8f30: ch = MXMISD:RET 0x17f7480, 0x17f7480:1
Optimized lowered selection DAG: BB#3 'isZero:return'
SelectionDAG has 7 nodes:
0x17d0fb0: ch = EntryToken [ORD=6]
0x17d0fb0: <multiple use>
0x17f6c80: i32 = Register %R2
0x17d0fb0: <multiple use>
0x17f6b80: i32 = FrameIndex<0> [ORD=6]
0x17f7280: i32 = undef [ORD=6]
0x17f6780: i32,ch = load 0x17d0fb0, 0x17f6b80, 0x17f7280<LD4[%retval]> [ORD=6]
0x17f7480: ch,glue = CopyToReg 0x17d0fb0, 0x17f6c80, 0x17f6780
0x17f7480: <multiple use>
0x17f7480: <multiple use>
0x17f8f30: ch = MXMISD:RET 0x17f7480, 0x17f7480:1
Legally typed node: 0x17f6c80: i32 = Register %R2 [ID=0]
Legally typed node: 0x17f7280: i32 = undef [ORD=6] [ID=0]
Legally typed node: 0x17f6b80: i32 = FrameIndex<0> [ORD=6] [ID=0]
Legally typed node: 0x17d0fb0: ch = EntryToken [ORD=6] [ID=0]
Legally typed node: 0x17f6780: i32,ch = load 0x17d0fb0, 0x17f6b80, 0x17f7280<LD4[%retval]> [ORD=6] [ID=0]
Legally typed node: 0x17f7480: ch,glue = CopyToReg 0x17d0fb0, 0x17f6c80, 0x17f6780 [ID=0]
Legally typed node: 0x17f8f30: ch = MXMISD:RET 0x17f7480, 0x17f7480:1 [ID=0]
Legally typed node: 0x7fff9df7bd30: ch = handlenode 0x17f8f30 [ID=0]
Type-legalized selection DAG: BB#3 'isZero:return'
SelectionDAG has 7 nodes:
0x17d0fb0: ch = EntryToken [ORD=6] [ID=-3]
0x17d0fb0: <multiple use>
0x17f6c80: i32 = Register %R2 [ID=-3]
0x17d0fb0: <multiple use>
0x17f6b80: i32 = FrameIndex<0> [ORD=6] [ID=-3]
0x17f7280: i32 = undef [ORD=6] [ID=-3]
0x17f6780: i32,ch = load 0x17d0fb0, 0x17f6b80, 0x17f7280<LD4[%retval]> [ORD=6] [ID=-3]
0x17f7480: ch,glue = CopyToReg 0x17d0fb0, 0x17f6c80, 0x17f6780 [ID=-3]
0x17f7480: <multiple use>
0x17f7480: <multiple use>
0x17f8f30: ch = MXMISD:RET 0x17f7480, 0x17f7480:1 [ID=-3]
Legalized selection DAG: BB#3 'isZero:return'
SelectionDAG has 7 nodes:
0x17d0fb0: ch = EntryToken [ORD=6] [ID=0]
0x17d0fb0: <multiple use>
0x17f6c80: i32 = Register %R2 [ID=3]
0x17d0fb0: <multiple use>
0x17f6b80: i32 = FrameIndex<0> [ORD=6] [ID=1]
0x17f7280: i32 = undef [ORD=6] [ID=2]
0x17f6780: i32,ch = load 0x17d0fb0, 0x17f6b80, 0x17f7280<LD4[%retval]> [ORD=6] [ID=4]
0x17f7480: ch,glue = CopyToReg 0x17d0fb0, 0x17f6c80, 0x17f6780 [ID=5]
0x17f7480: <multiple use>
0x17f7480: <multiple use>
0x17f8f30: ch = MXMISD:RET 0x17f7480, 0x17f7480:1 [ID=6]
Optimized legalized selection DAG: BB#3 'isZero:return'
SelectionDAG has 7 nodes:
0x17d0fb0: ch = EntryToken [ORD=6] [ID=0]
0x17d0fb0: <multiple use>
0x17f6c80: i32 = Register %R2 [ID=3]
0x17d0fb0: <multiple use>
0x17f6b80: i32 = FrameIndex<0> [ORD=6] [ID=1]
0x17f7280: i32 = undef [ORD=6] [ID=2]
0x17f6780: i32,ch = load 0x17d0fb0, 0x17f6b80, 0x17f7280<LD4[%retval]> [ORD=6] [ID=4]
0x17f7480: ch,glue = CopyToReg 0x17d0fb0, 0x17f6c80, 0x17f6780 [ID=5]
0x17f7480: <multiple use>
0x17f7480: <multiple use>
0x17f8f30: ch = MXMISD:RET 0x17f7480, 0x17f7480:1 [ID=6]
===== Instruction selection begins: BB#3 'return'
ISEL: Starting pattern match on root node: 0x17f8f30: ch = MXMISD:RET 0x17f7480, 0x17f7480:1 [ID=6]
Skipped scope entry (due to false predicate) at index 2, continuing at 59
Skipped scope entry (due to false predicate) at index 61, continuing at 219
Skipped scope entry (due to false predicate) at index 220, continuing at 261
Skipped scope entry (due to false predicate) at index 262, continuing at 303
Skipped scope entry (due to false predicate) at index 304, continuing at 345
Skipped scope entry (due to false predicate) at index 346, continuing at 387
Skipped scope entry (due to false predicate) at index 388, continuing at 429
Skipped scope entry (due to false predicate) at index 430, continuing at 471
Skipped scope entry (due to false predicate) at index 472, continuing at 513
Skipped scope entry (due to false predicate) at index 514, continuing at 559
Skipped scope entry (due to false predicate) at index 560, continuing at 605
Skipped scope entry (due to false predicate) at index 606, continuing at 651
Skipped scope entry (due to false predicate) at index 652, continuing at 685
Skipped scope entry (due to false predicate) at index 686, continuing at 718
Morphed node: 0x17f8f30: ch = RET 0x17f7480
ISEL: Match complete!
ISEL: Starting pattern match on root node: 0x17f6780: i32,ch = load 0x17d0fb0, 0x17f6b80, 0x17f7280<LD4[%retval]> [ORD=6] [ID=4]
Morphed node: 0x17f6780: i32,ch = LDWi13 0x17f7380, 0x17f6d80, 0x17d0fb0<Mem:LD4[%retval]> [ORD=6]
ISEL: Match complete!
===== Instruction selection ends:
Selected selection DAG: BB#3 'isZero:return'
SelectionDAG has 7 nodes:
0x17d0fb0: ch = EntryToken [ORD=6]
0x17d0fb0: <multiple use>
0x17f6c80: i32 = Register %R2
0x17f7380: i32 = TargetFrameIndex<0>
0x17f6d80: i32 = TargetConstant<0>
0x17d0fb0: <multiple use>
0x17f6780: i32,ch = LDWi13 0x17f7380, 0x17f6d80, 0x17d0fb0<Mem:LD4[%retval]> [ORD=6]
0x17f7480: ch,glue = CopyToReg 0x17d0fb0, 0x17f6c80, 0x17f6780
0x17f8f30: ch = RET 0x17f7480
********** List Scheduling BB#3 'return' **********
SU(0): 0x17f8f30: ch = RET 0x17f7480 [ID=0]
# preds left : 1
# succs left : 0
# rdefs left : 0
Latency : 1
Depth : 0
Height : 0
Predecessors:
ch SU(1): Latency=1
SU(1): 0x17f7480: ch,glue = CopyToReg 0x17d0fb0, 0x17f6c80, 0x17f6780 [ID=1]
# preds left : 1
# succs left : 1
# rdefs left : 0
Latency : 1
Depth : 0
Height : 0
Predecessors:
val SU(2): Latency=1
Successors:
ch SU(0): Latency=1
SU(2): 0x17f6780: i32,ch = LDWi13 0x17f7380, 0x17f6d80, 0x17d0fb0<Mem:LD4[%retval]> [ORD=6] [ID=2]
# preds left : 0
# succs left : 1
# rdefs left : 1
Latency : 1
Depth : 0
Height : 0
Successors:
val SU(1): Latency=1
Examining Available:
Height 0: SU(0): 0x17f8f30: ch = RET 0x17f7480 [ID=0]
*** Scheduling [0]: SU(0): 0x17f8f30: ch = RET 0x17f7480 [ID=0]
Examining Available:
Height 1: SU(1): 0x17f7480: ch,glue = CopyToReg 0x17d0fb0, 0x17f6c80, 0x17f6780 [ID=1]
*** Scheduling [1]: SU(1): 0x17f7480: ch,glue = CopyToReg 0x17d0fb0, 0x17f6c80, 0x17f6780 [ID=1]
GPRegs: 1 / 0
Examining Available:
Height 2: SU(2): 0x17f6780: i32,ch = LDWi13 0x17f7380, 0x17f6d80, 0x17d0fb0<Mem:LD4[%retval]> [ORD=6] [ID=2]
*** Scheduling [2]: SU(2): 0x17f6780: i32,ch = LDWi13 0x17f7380, 0x17f6d80, 0x17d0fb0<Mem:LD4[%retval]> [ORD=6] [ID=2]
*** Final schedule ***
SU(2): 0x17f6780: i32,ch = LDWi13 0x17f7380, 0x17f6d80, 0x17d0fb0<Mem:LD4[%retval]> [ORD=6] [ID=2]
SU(1): 0x17f7480: ch,glue = CopyToReg 0x17d0fb0, 0x17f6c80, 0x17f6780 [ID=1]
SU(0): 0x17f8f30: ch = RET 0x17f7480 [ID=0]
Total amount of phi nodes to update: 0
# Machine code for function isZero: SSA
Frame Objects:
fi#0: size=4, align=4, at location [SP]
fi#1: size=4, align=4, at location [SP]
Function Live Ins: %R2 in %vreg0
Function Live Outs: %R2
0B BB#0: derived from LLVM BB %entry
Live Ins: %R2
16B %vreg0<def> = COPY %R2; GPRegs:%vreg0
32B STWi13 <fi#1>, 0, %vreg0; mem:ST4[%a.addr] GPRegs:%vreg0
48B %vreg1<def> = CMPri %vreg0, 0; CondRegs:%vreg1 GPRegs:%vreg0
64B BRcondrel %vreg1<kill>, <BB#2>; CondRegs:%vreg1
80B BRrel <BB#1>
Successors according to CFG: BB#1(12) BB#2(20)
96B BB#1: derived from LLVM BB %if.then
Predecessors according to CFG: BB#0
112B %vreg3<def> = MOVri 1; GPRegs:%vreg3
128B STWi13 <fi#0>, 0, %vreg3<kill>; mem:ST4[%retval] GPRegs:%vreg3
144B BRrel <BB#3>
Successors according to CFG: BB#3
160B BB#2: derived from LLVM BB %if.else
Predecessors according to CFG: BB#0
176B %vreg2<def> = MOVri 0; GPRegs:%vreg2
192B STWi13 <fi#0>, 0, %vreg2<kill>; mem:ST4[%retval] GPRegs:%vreg2
Successors according to CFG: BB#3
208B BB#3: derived from LLVM BB %return
Predecessors according to CFG: BB#2 BB#1
224B %vreg4<def> = LDWi13 <fi#0>, 0; mem:LD4[%retval] GPRegs:%vreg4
240B %R2<def> = COPY %vreg4; GPRegs:%vreg4
256B RET
# End machine code for function isZero.
********** Stack Coloring **********
********** Function: isZero
Found 0 markers and 2 slots
Slot structure:
Slot #0 - 4 bytes.
Slot #1 - 4 bytes.
Total Stack size: 8 bytes
Will not try to merge slots.
Removed 0 markers.
DeadMachineInstructionElim: DELETING: BRrel <BB#3>
DeadMachineInstructionElim: DELETING: BRrel <BB#1>
DeadMachineInstructionElim: DELETING: BRcondrel %vreg1<kill>, <BB#2>; CondRegs:%vreg1
DeadMachineInstructionElim: DELETING: %vreg1<def> = CMPri %vreg0, 0; CondRegs:%vreg1 GPRegs:%vreg0
******** Pre-regalloc Machine LICM: isZero ********
Entering: entry
Entering: if.else
Exiting: if.else
Entering: return
Exiting: return
Entering: if.then
Exiting: if.then
Exiting: entry
******** Machine Sinking ********
********** PROCESS IMPLICIT DEFS **********
********** Function: isZero
********** REWRITING TWO-ADDR INSTRS **********
********** Function: isZero
# Machine code for function isZero: Post SSA
Frame Objects:
fi#0: size=4, align=4, at location [SP]
fi#1: size=4, align=4, at location [SP]
Function Live Ins: %R2 in %vreg0
Function Live Outs: %R2
0B BB#0: derived from LLVM BB %entry
Live Ins: %R2
16B %vreg0<def> = COPY %R2<kill>; GPRegs:%vreg0
32B STWi13 <fi#1>, 0, %vreg0<kill>; mem:ST4[%a.addr] GPRegs:%vreg0
Successors according to CFG: BB#1(12) BB#2(20)
48B BB#1: derived from LLVM BB %if.then
Predecessors according to CFG: BB#0
64B %vreg3<def> = MOVri 1; GPRegs:%vreg3
80B STWi13 <fi#0>, 0, %vreg3<kill>; mem:ST4[%retval] GPRegs:%vreg3
Successors according to CFG: BB#3
96B BB#2: derived from LLVM BB %if.else
Predecessors according to CFG: BB#0
112B %vreg2<def> = MOVri 0; GPRegs:%vreg2
128B STWi13 <fi#0>, 0, %vreg2<kill>; mem:ST4[%retval] GPRegs:%vreg2
Successors according to CFG: BB#3
144B BB#3: derived from LLVM BB %return
Predecessors according to CFG: BB#2 BB#1
160B %vreg4<def> = LDWi13 <fi#0>, 0; mem:LD4[%retval] GPRegs:%vreg4
176B %R2<def> = COPY %vreg4<kill>; GPRegs:%vreg4
192B RET %R2<imp-use,kill>
# End machine code for function isZero.
********** COMPUTING LIVE INTERVALS **********
********** Function: isZero
BB#0: # derived from entry
16B %vreg0<def> = COPY %R2<kill>; GPRegs:%vreg0
register: %vreg0 +[16r,32r:0)
32B STWi13 <fi#1>, 0, %vreg0<kill>; mem:ST4[%a.addr] GPRegs:%vreg0
BB#1: # derived from if.then
64B %vreg3<def> = MOVri 1; GPRegs:%vreg3
register: %vreg3 +[64r,80r:0)
80B STWi13 <fi#0>, 0, %vreg3<kill>; mem:ST4[%retval] GPRegs:%vreg3
BB#2: # derived from if.else
112B %vreg2<def> = MOVri 0; GPRegs:%vreg2
register: %vreg2 +[112r,128r:0)
128B STWi13 <fi#0>, 0, %vreg2<kill>; mem:ST4[%retval] GPRegs:%vreg2
BB#3: # derived from return
160B %vreg4<def> = LDWi13 <fi#0>, 0; mem:LD4[%retval] GPRegs:%vreg4
register: %vreg4 +[160r,176r:0)
176B %R2<def> = COPY %vreg4<kill>; GPRegs:%vreg4
192B RET %R2<imp-use,kill>
Computing live-in reg-units in ABI blocks.
0B BB#0 R2#0
Created 1 new intervals.
********** INTERVALS **********
R2 = [0B,16r:0)[176r,192r:1) 0 at 0B-phi 1 at 176r
%vreg0 = [16r,32r:0) 0 at 16r
%vreg2 = [112r,128r:0) 0 at 112r
%vreg3 = [64r,80r:0) 0 at 64r
%vreg4 = [160r,176r:0) 0 at 160r
RegMasks:
********** MACHINEINSTRS **********
# Machine code for function isZero: Post SSA
Frame Objects:
fi#0: size=4, align=4, at location [SP]
fi#1: size=4, align=4, at location [SP]
Function Live Ins: %R2 in %vreg0
Function Live Outs: %R2
0B BB#0: derived from LLVM BB %entry
Live Ins: %R2
16B %vreg0<def> = COPY %R2; GPRegs:%vreg0
32B STWi13 <fi#1>, 0, %vreg0<kill>; mem:ST4[%a.addr] GPRegs:%vreg0
Successors according to CFG: BB#1(12) BB#2(20)
48B BB#1: derived from LLVM BB %if.then
Predecessors according to CFG: BB#0
64B %vreg3<def> = MOVri 1; GPRegs:%vreg3
80B STWi13 <fi#0>, 0, %vreg3<kill>; mem:ST4[%retval] GPRegs:%vreg3
Successors according to CFG: BB#3
96B BB#2: derived from LLVM BB %if.else
Predecessors according to CFG: BB#0
112B %vreg2<def> = MOVri 0; GPRegs:%vreg2
128B STWi13 <fi#0>, 0, %vreg2<kill>; mem:ST4[%retval] GPRegs:%vreg2
Successors according to CFG: BB#3
144B BB#3: derived from LLVM BB %return
Predecessors according to CFG: BB#2 BB#1
160B %vreg4<def> = LDWi13 <fi#0>, 0; mem:LD4[%retval] GPRegs:%vreg4
176B %R2<def> = COPY %vreg4<kill>; GPRegs:%vreg4
192B RET %R2<imp-use>
# End machine code for function isZero.
********** COMPUTING LIVE DEBUG VARIABLES: isZero **********
********** DEBUG VARIABLES **********
********** SIMPLE REGISTER COALESCING **********
********** Function: isZero
********** JOINING INTERVALS ***********
entry:
16B %vreg0<def> = COPY %R2; GPRegs:%vreg0
Considering merging %vreg0 with %R2
Can only merge into reserved registers.
if.then:
if.else:
return:
176B %R2<def> = COPY %vreg4<kill>; GPRegs:%vreg4
Considering merging %vreg4 with %R2
Can only merge into reserved registers.
Trying to inflate 0 regs.
********** INTERVALS **********
R2 = [0B,16r:0)[176r,192r:1) 0 at 0B-phi 1 at 176r
%vreg0 = [16r,32r:0) 0 at 16r
%vreg2 = [112r,128r:0) 0 at 112r
%vreg3 = [64r,80r:0) 0 at 64r
%vreg4 = [160r,176r:0) 0 at 160r
RegMasks:
********** MACHINEINSTRS **********
# Machine code for function isZero: Post SSA
Frame Objects:
fi#0: size=4, align=4, at location [SP]
fi#1: size=4, align=4, at location [SP]
Function Live Ins: %R2 in %vreg0
Function Live Outs: %R2
0B BB#0: derived from LLVM BB %entry
Live Ins: %R2
16B %vreg0<def> = COPY %R2; GPRegs:%vreg0
32B STWi13 <fi#1>, 0, %vreg0<kill>; mem:ST4[%a.addr] GPRegs:%vreg0
Successors according to CFG: BB#1(12) BB#2(20)
48B BB#1: derived from LLVM BB %if.then
Predecessors according to CFG: BB#0
64B %vreg3<def> = MOVri 1; GPRegs:%vreg3
80B STWi13 <fi#0>, 0, %vreg3<kill>; mem:ST4[%retval] GPRegs:%vreg3
Successors according to CFG: BB#3
96B BB#2: derived from LLVM BB %if.else
Predecessors according to CFG: BB#0
112B %vreg2<def> = MOVri 0; GPRegs:%vreg2
128B STWi13 <fi#0>, 0, %vreg2<kill>; mem:ST4[%retval] GPRegs:%vreg2
Successors according to CFG: BB#3
144B BB#3: derived from LLVM BB %return
Predecessors according to CFG: BB#2 BB#1
160B %vreg4<def> = LDWi13 <fi#0>, 0; mem:LD4[%retval] GPRegs:%vreg4
176B %R2<def> = COPY %vreg4<kill>; GPRegs:%vreg4
192B RET %R2<imp-use>
# End machine code for function isZero.
********** DEBUG VARIABLES **********
********** Compute Spill Weights **********
********** Function: isZero
********** GREEDY REGISTER ALLOCATION **********
********** Function: isZero
selectOrSplit GPRegs:%vreg0 [16r,32r:0) 0 at 16r
AllocationOrder(GPRegs) = [ %R1 %R2 %R3 %R4 %R5 %R20 %R21 %R22 %R23 %R24 %R25 %R26 %R27 %R28 %R29 %R6 %R7 %R8 %R9 %R10 %R11 %R12 %R13 %R14 %R15 %R16 %R17 %R18 %R19 ]
assigning %vreg0 to %R2: R2
selectOrSplit GPRegs:%vreg4 [160r,176r:0) 0 at 160r
assigning %vreg4 to %R2: R2
selectOrSplit GPRegs:%vreg2 [112r,128r:0) 0 at 112r
assigning %vreg2 to %R1: R1
selectOrSplit GPRegs:%vreg3 [64r,80r:0) 0 at 64r
assigning %vreg3 to %R1: R1
********** REWRITE VIRTUAL REGISTERS **********
********** Function: isZero
********** REGISTER MAP **********
[%vreg0 -> %R2] GPRegs
[%vreg2 -> %R1] GPRegs
[%vreg3 -> %R1] GPRegs
[%vreg4 -> %R2] GPRegs
0B BB#0: derived from LLVM BB %entry
Live Ins: %R2
16B %vreg0<def> = COPY %R2; GPRegs:%vreg0
32B STWi13 <fi#1>, 0, %vreg0<kill>; mem:ST4[%a.addr] GPRegs:%vreg0
Successors according to CFG: BB#1(12) BB#2(20)
> %R2<def> = COPY %R2
Deleting identity copy.
> STWi13 <fi#1>, 0, %R2<kill>; mem:ST4[%a.addr]
48B BB#1: derived from LLVM BB %if.then
Predecessors according to CFG: BB#0
64B %vreg3<def> = MOVri 1; GPRegs:%vreg3
80B STWi13 <fi#0>, 0, %vreg3<kill>; mem:ST4[%retval] GPRegs:%vreg3
Successors according to CFG: BB#3
> %R1<def> = MOVri 1
> STWi13 <fi#0>, 0, %R1<kill>; mem:ST4[%retval]
96B BB#2: derived from LLVM BB %if.else
Predecessors according to CFG: BB#0
112B %vreg2<def> = MOVri 0; GPRegs:%vreg2
128B STWi13 <fi#0>, 0, %vreg2<kill>; mem:ST4[%retval] GPRegs:%vreg2
Successors according to CFG: BB#3
> %R1<def> = MOVri 0
> STWi13 <fi#0>, 0, %R1<kill>; mem:ST4[%retval]
144B BB#3: derived from LLVM BB %return
Predecessors according to CFG: BB#2 BB#1
160B %vreg4<def> = LDWi13 <fi#0>, 0; mem:LD4[%retval] GPRegs:%vreg4
176B %R2<def> = COPY %vreg4<kill>; GPRegs:%vreg4
192B RET %R2<imp-use>
> %R2<def> = LDWi13 <fi#0>, 0; mem:LD4[%retval]
> %R2<def> = COPY %R2<kill>
Deleting identity copy.
> RET %R2<imp-use>
********** EMITTING LIVE DEBUG VARIABLES **********
********** Stack Slot Coloring **********
********** Function: isZero
******** Post-regalloc Machine LICM: isZero ********
alloc FI(0) at SP[-4]
alloc FI(1) at SP[-8]
TryTailMergeBlocks: BB#1, BB#3
Looking for common tails of at least 3 instructions
Merging into block: BB#0: derived from LLVM BB %entry
Live Ins: %R2
%R0<def> = SUBri %R0, 8
STWi13 %R29, 8, %R2<kill>; mem:ST4[%a.addr]
Successors according to CFG: BB#1(12)
>From MBB: BB#1: derived from LLVM BB %if.then
Predecessors according to CFG: BB#0
%R1<def> = MOVri 1
STWi13 %R29, 4, %R1<kill>; mem:ST4[%retval]
Removing MBB: BB#1: derived from LLVM BB %if.then
Removing MBB: BB#2: derived from LLVM BB %if.else
%R1<def> = MOVri 0
STWi13 %R29, 4, %R1<kill>; mem:ST4[%retval]
Successors according to CFG: BB#3
Removing MBB: BB#3: derived from LLVM BB %return
%R2<def> = LDWi13 %R29, 4; mem:LD4[%retval]
%R0<def> = ADDri %R0, 8
RET %R2<imp-use>
Machine Function
********** EXPANDING POST-RA PSEUDO INSTRS **********
********** Function: isZero
RPO[BB#0 derived from LLVM BB entry] = 1
POT: BB#0 derived from LLVM BB entry
doLoop(BB#0 derived from LLVM BB entry, BB#0 derived from LLVM BB entry)
doBlock(BB#0 derived from LLVM BB entry)
Frequency(BB#0 derived from LLVM BB entry) = 0
Frequency(BB#0 derived from LLVM BB entry) = 1024
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