[LLVMdev] Problems with 64-bit register operands of inline asm on ARM

[Måns Rullgård]

Jim Grosbach <grosbach at apple.com> writes:

> On Mar 13, 2013, at 11:01 AM, Renato Golin <renato.golin at linaro.org>
> wrote:
>
>> On 13 March 2013 17:57, Jim Grosbach <grosbach at apple.com> wrote:
>>> It seems to me that LLVM doesn’t parse the inline asm body. It just
>>> checks the constraints, (ie. Input/output interface). During ASM
>>> writing, it then binding those constraints to placeholders like %0,
>>> %1.
>> This is correct.
>> 
>> Ok, so maybe checking all possible ways to require paired registers
>> is not such a bad idea after all.
>> 
>
> The constraints are the right way to do it. There shouldn't be any
> magic beyond that.

Since there is no special operand constraint for a register pair, there
is no way to tell at that level.

GCC has (implicitly) defined 64-bit register operands as residing in
even/odd pairs, thus leaving inline asm free to make all manner of
assumptions based on this.  The only way I see to guarantee
compatibility is to mimic the gcc behaviour here.  It may be slightly
suboptimal in a few cases, but it's the safe choice.

-- 
Måns Rullgård
mans at mansr.com