[LLVMdev] Bug in visitSIGN_EXTEND in DAGCombiner.cpp?

[Nadav Rotem]

Hi Richard, 

> 
> I did… It originates from an icmp ne <2x i8>, zero initializer followed by a sext of the result 2x i1 to 2x i8. When we visit the SIGN_EXTEND, we generate the ISD::SELECT even though the selector and both operands are vectors.
> 

It sounds like a bug in the dag combine optimization. If you send me the line number I will take a look.  

>> We should probably add an assert in SelectionDAG::getNode().
> 
>> 
>>> I've tried a local change that cures this particular assert, but uncovers another assert later, so I'm a bit uncertain if I'm heading off in the wrong direction.
>> 

Adding assertions to getNode is the right thing to do. I am not sure that it will solve your problem, but it will help us some some problems. 

>> I think that replacing SELECT with VSELECT is the right thing to do. 
> 
> VT.isVector() ? ISD::VSELECT : ISD::SELECT in lieu of the fixed ISD::SELECT seems to do the trick for me. Except that it sometimes hits the assert in ExpandVSELECT…

Okay. Which assertion in ExpandVSELECT fail ?  Maybe our assumptions there are incorrect. 

> 
>>> The subsequent assert comes in ExpandVSELECT, which expects (for no good reason as far as I can tell) that the "mask" (really the 'selector') and the operands will be the same width, rather than trying to make them the same width (in our problem cases, the mask is an i32 produced from getSetCCResultType() and the ops are i8 or i16 - all vectors of the same length, of course.)
>> 
>> If I remember correctly the trick of expanding VSELECT into a sequence of XOR/AND/OR only works if the mask is known to be all-one or all-zero. 
> 
> Well, that's not a problem since the mask was generated from a sign extend from an i1… ;-) The problem comes about because the i32 mask and i8 or i16 operands are different widths and expandVSELECT is not equipped to deal with that case.

Can you write down the input SDNode ?  What types are inputs ? 

Thanks,
Nadav
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