[LLVMdev] [RFC] TileGX, a new backend for Tilera's many core processor

[Jiong Wang]

Hi all,

Updated the patches for TILE-Gx backend:

1. added initial regression tests for tilegx codegen.
2. added initial regression tests for MC Layer.
3. fixed those commenting style issues.

please review, thanks.

I have tried to understand the new backend requirement for LLVM from the 
mailiing list archive,
it's sure TILE-Gx backend will be actively maintained & improved, it's 
not a code-drop'd backend :)

please feel free to give suggestions on how could this target get 
included in LLVM mainline.

=== Backend Intro ===

TILE-Gx is a VLIW architecture with 64-bit registers, 64-bit address space,
and 64-bit instructions. TILE-Gx has load-store architecture ISAs.

More information on the architectures is available at
http://www.tilera.com/scm/docs/index.html.

features supported
---
1. general function.
2. PIC/TLS/JumpTable.
3. Instructoin Bundling for VLIW.
4. Asm Parser (no support for bundle syntax .s, need modification on generic MC code to support this)
5. MC Layer (support instruction bundle), MCJIT support.

regression result
---
Expected Passes : 13318
Expected Failures : 78
Unsupported Tests : 68
Unexpected Failures: 32
(20 failures are caused by lacking old JIT support)

test-suite result
---
Expected Passes : 949
Unexpected Failures: 17
(all 17 failures has the same output as tilegx gcc,
  most of them are about float precision issue)

---
Regards,
Jiong
Tilera Corporation

于 2013/3/2 9:19, Jiong Wang 写道:
> On 03/02/2013 04:50 AM, Dmitri Gribenko wrote:
>> You also need tests for Clang bits, too.
>>
>> Mechanical issues:
>>
>> +/// getTileRegisterNumbering - Given the enum value for some register,
>> +/// return the number that it corresponds to.
>>
>> Please don't duplicate function and class name in comments. Existing
>> code does this, but current style guidelines advise not to.
>>
>> http://llvm.org/docs/CodingStandards.html#doxygen-use-in-documentation-comments 
>>
>>
>> + BuildMI(MBB, I, I->getDebugLoc(), TII->get(Tile::ADD)
>> + ,I->getOperand(0).getReg())
>> + .addReg(Tile::ZERO)
>> + .addReg(src_sp);
>>
>> +unsigned TileInstrInfo::
>> +isLoadFromStackSlot(const MachineInstr *MI, int &FrameIndex) const
>>
>> You have some weird formatting here and there. You could try
>> clang-format to pretty-print your code automatically.
>>
>> The patch is also missing documentation bits. At the very least, a
>> paragraph for ReleaseNotes.
>>
>> + // save lr to caller's stack reserve slot 0
>>
>> Comments should start with a capital letter and end with a full stop.
>
> Hi Damitri,
>
> thanks for your time to review, I will fix these things according
> to llvm coding style doc.
>
> ---
> Regards,
> Jiong
>
>>
>> Dmitri
>>
>
>

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