[LLVMdev] tablegen question

[Micah Villmow]

Thanks tom. I was hoping I wouldn't have to do that, it's a lot easier to model instructions the same as the ISA than have to hack things up. :(

Micah

-----Original Message-----
From: Tom Stellard [mailto:tom at stellard.net] 
Sent: Tuesday, June 25, 2013 9:20 AM
To: Micah Villmow
Cc: llvmdev at cs.uiuc.edu
Subject: Re: [LLVMdev] tablegen question

Hi Micah,

On Tue, Jun 25, 2013 at 03:47:14PM +0000, Micah Villmow wrote:
> How do you specify in a tablegen pattern that all destination registers are also source registers? I know I could just duplicate them, but I was wondering if there was a way it could be done without doing this. Basically an inplace operation.
> 

I'm not sure if there is a good way to do this.  The V_INTERP_P2_F32 instruction for SI has operands that are both inputs and outputs, but we model this by duplicating the operands adding a constraint.

You may be able to define an instruction with duplicate operands and then lower it to one without duplicates using a custom inserter, but I'm not sure if that is really any better.

-Tom

> So for example, take a hypothetical swap w/ sqrt.
> if I had swap $ds0, $ds1
> 
> which swaps ds1 and ds0 and applies sqrt on the registers afterwards.
> 
> Micah

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