[LLVMdev] Register Class assignment for integer and pointer types

杨勇勇 triple.yang at gmail.com
Sun Jun 23 20:50:30 PDT 2013


2013/6/23 David Chisnall <David.Chisnall at cl.cam.ac.uk>

> Hi,
>
> In our version of LLVM, we've added different-sized iPTR* types, so we
> have an iPTR256 for our fat pointers.  This causes some problems with
> constraints, because the way that TableGen resolves constraints is not
> expected to handle multiple pointer types.  We've added a flag that can be
> set on a per-backend basis to turn this off.


> Our problem is perhaps a bit different form yours, as our pointers must be
> loaded and manipulated via special instructions, they can not use the
> integer instructions or registers.
>

In our processor, addresses (i.e. pointers) must be assigned to a specific
kind of registers before it can be used for memory access, which is the
common part between yours and ours.

Here are 2 possible solutions for our problem:
1. constrain instruction selection.
1.1  use    "addRegisterClass(MVT::iPTR,  XXX::PTRRegClass);" to bind
pointers and their register class.
1.2  add a pass to transform ISelDAG before instruction selection. Since we
can determine from opcodes whether an operation can only take address
registers as its input operands, we replace i32 with iPTR if so, and insert
reg-reg move operations if necessary. For example, (load reg,  addr:i32)
means we read at 'addr' to fill 'reg'. Here, we modify it to (load reg,
 addr:iPTR).
1.3  in XXXInstrInfo.td, we give (load  reg,   iPTR:$addr) to match pattern.
1.4  and finally we "hope" default register allocator do the proper thing.

2. add an annotation pass before register allocation.
2.1  we treat both integer and pointer as i32, and hence there is just
"addRegisterClass(MVT::i32,  XXX::I32RegClass);"
2.2  before register allocation we annote operands if they must reside in
address register.
2.3  register allocation assigns register class according to annotations
mentioned in 2.2, and perhaps a custom register allocator has to be
implemented.

Which way do you think is more feasible?

Regards.



> David
>
> On 23 Jun 2013, at 15:49, 杨勇勇 <triple.yang at gmail.com> wrote:
>
> > David, thanks for your immediate response.
> >
> > Since iPTR is a reserved type for tablegen internal use, can you make a
> further explanation?
> >
> > On the other hand, it can be simply treated as a register class
> assignment problem during register allocation.
> > Assume both pointer and integet have a 32 bit width. backend handles it
> just as to i32. When it performs register allocation, it can retrieve from
> target constraint information about which register class is valid for a
> operand, and this is determined by which instruction consumes the operand.
> >
> > So is there a convienient way to constrain register class assignment,
> like a tablegen interface or something else?
> >
> > Regards.
> >
> > 2013/6/21 David Chisnall <David.Chisnall at cl.cam.ac.uk>
> > We also have this problem, and have added iPTR types to the back end.
>  Our pointers are actually fat pointers, so this also requires tweaking
> some optimisations (for example, things like to turn GEPs with 64-bit
> offsets into pointer-sized offsets, but our pointers are larger than any
> integer type that we support...).  Most of the changes are a bit ugly, and
> I'm loath to upstream them without an in-tree target that has these
> requirements, or they will be hard for anyone else to keep working.
> >
> > David
> >
> > On 21 Jun 2013, at 06:00, 杨勇勇 <triple.yang at gmail.com> wrote:
> >
> > > llvm code generator lowers both integer and pointer types into
> ixx(say, i16, i32, i64, ...). This make senses for some optimizations.
> > >
> > > However, integer registers and pointer registers is expilicitly
> distinguished from each other for some architectures, like TriCore,
> Blackfin, and our lab prototype dsp, which accelerates address computation
> and memory access.
> > >
> > > I have already read this mail thread:
> http://lists.cs.uiuc.edu/pipermail/llvmdev/2009-May/022142.html , and I
> am wondering how is the progress about it.
> > >
> > > Thanks.
> > >
> > > --
> > > 杨勇勇 (Yang Yong-Yong)
> > > _______________________________________________
> > > LLVM Developers mailing list
> > > LLVMdev at cs.uiuc.edu         http://llvm.cs.uiuc.edu
> > > http://lists.cs.uiuc.edu/mailman/listinfo/llvmdev
> >
> >
> >
> >
> > --
> > 杨勇勇 (Yang Yong-Yong)
>
>


-- 
杨勇勇 (Yang Yong-Yong)
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