[LLVMdev] A question w.r.t fence instruction vs. noalias pointer

[Guo, Xiaoyi]

I mean something like a target-specific fence machine instruction which forces ordering of all loads/stores. I want to clarify the meaning of "noalias" in this case. Is the fence machine instruction considered "touching" all memory and thus breaks the "noalias" contract?

Xiaoyi

From: Eli Friedman [mailto:eli.friedman at gmail.com]
Sent: Wednesday, June 12, 2013 8:08 PM
To: Guo, Xiaoyi
Cc: LLVM Dev
Subject: Re: [LLVMdev] A question w.r.t fence instruction vs. noalias pointer

On Wed, Jun 12, 2013 at 7:28 PM, Guo, Xiaoyi <Xiaoyi.Guo at amd.com<mailto:Xiaoyi.Guo at amd.com>> wrote:
So fence only forces ordering of atomic instructions.

Let me change my question then.

If I have a target-specific intrinsic which forces ordering of ordinary load/store instructions. Then should it also force ordering of load/stores to noalias pointers in caller functions?

So, something like 'asm volatile ("":::"memory")'?
LLVM can and will move noalias loads/stores across an asm statement like this; it assumes noalias means "nothing inside this function will touch the memory in question except accesses through this pointer".

-Eli
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