[LLVMdev] [PATCH] x86: disambiguate unqualified btr, bts

[Jevin Sweval]

http://www.cs.fsu.edu/~baker/devices/lxr/http/source/linux/arch/x86/include/asm/bitops.h#L68

Here is one example that I found. Are the inline assembly arguments
ambiguous in size?

-Jevin

Sent from my mobile device. Typos are par for the course.

On Jul 10, 2013, at 5:47 PM, Jim Grosbach <grosbach at apple.com> wrote:


On Jul 10, 2013, at 2:30 PM, Eric Christopher <echristo at gmail.com> wrote:

On Wed, Jul 10, 2013 at 2:08 PM, Ramkumar Ramachandra
<artagnon at gmail.com> wrote:

Jim Grosbach wrote:

To say that another way, is the assembler correctly diagnosing a previously
unnoticed problem in the project source code, or is the assembler not
behaving correctly according the the documented Intel assembly mnemonics?


Where are the authoritative instruction set pages?  If such a thing
were readily available, why are there gaps in the current
implementation?  A quick Googling gets me [1], but I can't say it's
authoritative.  What's important is that there certainly are
architectures where btr/bts are valid instructions, and they must be
supported.  btr/bts are certainly not invalid instructions that we're
bending over backwards to support, because linux.git/gas works with
them.

[1]: http://web.itu.edu.tr/kesgin/mul06/intel/index.html
_


The correct answer here is "Vol 2a of the Intel Reference Manual
available off of the Intel website”.


Yep, for Intel syntax that’s exactly right.

As far as whether or not we should support the instructions with a
lack of length mnemonic, I'm going to step back away from the
discussion. The Intel manuals support Intel syntax (which we also
support) which necessarily doesn't have length encodings for most
instructions, but AT&T syntax which gas uses (and llvm supports as
well) often has length specifiers for instructions.



The length specifier is, as I understand it, required when the instruction
references memory but is optional (and inferred from the registers) for the
register variants.

The best reference I know of for the AT&T syntax is:
http://docs.oracle.com/cd/E19253-01/817-5477/817-5477.pdf

That does raise a clarifying question here. Is the code you’re interested
in using Intel or AT&T syntax?

Also note that the question isn’t whether we should support the btr/bts
instructions. We absolutely must (and do). The question is whether we are
properly handling the un-suffixed mnemonic form of the assembly syntax.

Perhaps you can help by clarifying via explicit example what code you
believe should work but does that. Descriptions are great, but specifics
are better once we’re this deep into the details.

-Jim

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