[LLVMdev] introducing sign extending halfword loads into the LLVM IR

[Bjorn De Sutter]

done, bug 15057, hope I submitted it correctly ...

On 23 Jan 2013, at 22:29, Arnold Schwaighofer <aschwaighofer at apple.com> wrote:

> Hi Bjorn,
> 
> could you file a bug on llvm.org/bugs and cc me on it.
> 
> Thanks,
> Arnold
> 
> 
>> So it appears that also the ARM backend has a big problems with sign-extending loads.
>> 
>> I've compiled the following loop
>> 
>> short in[];
>> int out[];
>> int value;
>> 
>> for (i = 0; i < nr; i++) {
>>         value = in[i];
>>         if (value>2047)
>>                value = 2047;
>>         else if (value<-2048)
>>                value = -2048;
>>         out[i]=value;
>>  }
>> 
>> I used opt -O3 and llc -O3 -march=arm -regalloc=greedy, and here is the code that is generated for the loop body (and two instructions that set a loop-invariant mask beforehand), with some comments of mine:
>> 
>>        mov     r12, #255       
>>        orr     r12, r12, #65280  
>> LBB1_1:
>>        ldrsh   r3, [r1]               # loads a short that is sign-extended to 32 bits
>>        mov     r4, lr  
>>        cmp     r3, #2048       
>>        bge     .LBB1_3
>>        and     r4, r3, r12        # mask with 0xffff to convert to short again
>>        lsl     r4, r4, #16          # this lsl and the following 
>>        asr     r5, r4, #16        # asr implement sign-extension to 32 bits again ....
>>        ldr     r4, .LCPI1_1    
>>        cmn     r5, #2048       
>>        movge   r4, r3
>> .LBB1_3:
>>        str     r4, [r2, r0, lsl #2]
>>        add     r0, r0, #1      
>>        add     r1, r1, #2      
>>        cmp     r0, #67 
>>        blt     .LBB1_1
>> 
>> Clearly the sign-extensions are not handled correctly ...