[LLVMdev] Half Float fp16 Native Support

[Anton Korobeynikov]

> def FADD_H : NemaCorePseudo< (outs HGR16:$fd), (ins HGR16:$fs, HGR16:$ft),
> "add.h\t$fd, $fs, $ft", [(set (i16 HGR16:$fd),(i16 (f32_to_f16 (f32 (fadd
> (f32 (f16_to_f32 (i16 HGR16:$fs))),
> (f32 (f16_to_f32 (i16 HGR16:$ft))))))))]>;
>
> so i can have a half floating point add two half point variables and seems
> to work fine.
This does not look right. Note that you're matching f16_to_f32
intrinsics and friends. They are used for storage-only half FP stuff
and you're trying to match them instead of native fp16.

So, in short - you need to generate IR with proper fp16 arithmetics,
not via storage-only wrappers.

--
With best regards, Anton Korobeynikov
Faculty of Mathematics and Mechanics, Saint Petersburg State University