[LLVMdev] Sub-Register Allocation

[Jakob Stoklund Olesen]

On Jan 10, 2013, at 9:54 PM, Kenneth Waters <kwwaters at gmail.com> wrote:

> I have a pattern where I load the 16 bit portion of the register with 0, and then copy in the 8 bit portion.
> 
> def : Pat<(i16 (zextloadi8 addr:$src)),
>           (INSERT_SUBREG (MOV16id 0), (MOV8md addr:$src), sub_byte)>;
> 
> which produces working but odd assembly,
> 
> zext_i8_to_i16_simple   PROC            ; @zext_i8_to_i16_simple
> ; BB#0:
>         move.b  4(a7), d1
>         move.w  #0, d0
>         move.b  d1, d0
>         rts
> 
> Notice the extraneous use of d1, as
> 
> move.w #0, d0
> move.b 4(a7), d0
> 
> would work just as well.

LLVM's register coalescer and allocator don't try to reschedule instructions, which seems to be required here.

/jakob

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