[LLVMdev] MIScheduler / bundling

[Jonas Paulsson]

Hi,

I am looking at the Hexagon MI Scheduling and trying to adapt it to my target.

As far as I can see, Hexagon does not bundle the VLIW-bundles by calling bundleWithPred() on MIs of the completed cycle.

First of all, why is this not done? SlotIndexes seems to have at least some support for this, by calling getBundleStart() for each MI that is looked up.

A follow up question is then, how would I do this, so that the register allocator can work with bundle intervals?

Just calling bundleWithPred() gives
*** Bad machine code: Instruction inside bundle has a slot index ***

I would really appreciate if anyone let me know the plan on this,

Jonas Paulsson

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