[LLVMdev] Generate scalar SSE instructions instead of packed instructions

[Cameron McInally]

On Tue, Feb 26, 2013 at 3:38 PM, Nowicki, Tyler <tyler.nowicki at intel.com>wrote:

>  Thanks for the reply, they were very helpful.****
>
> ** **
>
> Is it enough to prevent BBVectorize from packing together double precision
> instructions? If a non-clang frontend is used, such as ISPC, is it possible
> that the IR may contain packed double instruction?
>

Yes, it could be possible that the IR includes packed SSE instructions.

I am not familiar with the ISPC frontend or Atom. But, in the general case,
a frontend could be using the SSE intrinsics, which can make use of packed
operands. For example:

>  def int_x86_sse_min_ps : GCCBuiltin<"__builtin_ia32_minps">,
>              Intrinsic<[llvm_v4f32_ty], [llvm_v4f32_ty,
>                         llvm_v4f32_ty], [IntrNoMem]>;

The compiler I work on has a proprietary vectorizer that runs before the
LLVM IR level. So, in our case, we have an extended set of proprietary
packed intrinsics similar to the GNU SSE built-ins.

-Cameron
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