[LLVMdev] Simulating instruction cache misses

[SArora]

Hi,

I am trying to analyze the instruction cache miss rate in different basic
blocks, and would like to know if there is any way to do this in LLVM. 

I am using the objdump file to find the size of various basic blocks and
their starting address. Now, when a basic block is encountered in a BB
iterator, I want to map it to one of the BBs I've collected from the dump,
and use the starting address and size to simulate a cache's behavior. For
instance, if a BB has size 32 and starting address as 1032, I'll generate
1032, 1036, 1040... and so on (assuming an instruction is 32 bits).

The problem is that the order in which BBs appear in the iterator doesn't
match with the order in which I've broken down the dump (which is
essentially storing the jmp targets and forming BBs later).
Any ideas to do this in a better way?

I'll really appreciate any help in this regard.

Thanks!



--
View this message in context: http://llvm.1065342.n5.nabble.com/Simulating-instruction-cache-misses-tp55094.html
Sent from the LLVM - Dev mailing list archive at Nabble.com.