[LLVMdev] DFAPacketizer

[Jonas Paulsson]

Hi,

I looked a bit through the mail archives, and found this question answered in Oct 2011 (see below). It is interesting to find this in the ARM backend, considering your answer. Can you give more information about for example is this a temporary deficiency in the DFAPacketizer? What is the IIC_iMOVi itinerary doing below?

Thanks,

Jonas


Thu Oct 6 15:11:25 CDT 2011:

Hello Hal.

> Is there a way to express a multiple pipeline itinerary using the
> current scheme
Yes, surely

> (maybe some trick with setting NextCycles = 0)?
Yep!

> Specifically, consider a case where a floating-point load simultaneously
> uses units from a floating-point pipeline and a load/store pipeline.
Look into ARM itineraries, they contain a decent amount of such examples.

[Head feb 2013:]
InstrItinData<IIC_iMOVi   , [InstrStage<1, [SW_DIS0, SW_DIS1, SW_DIS2], 0>,
                                        InstrStage<1, [SW_ALU0, SW_ALU1]>],
                                        [1]>,

________________________________
From: Anshuman Dasgupta [mailto:adasgupt at codeaurora.org]
Sent: Monday, February 11, 2013 7:19 PM
To: Jonas Paulsson; llvmdev at cs.uiuc.edu
Subject: RE: DFAPacketizer

Jonas,


At this point, the DFA packetizer models a simple VLIW architecture and does not accommodate multiple stages. That's the reason for the behavior you're seeing.


-Anshu


---
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation



From: llvmdev-bounces at cs.uiuc.edu<mailto:llvmdev-bounces at cs.uiuc.edu> [mailto:llvmdev-bounces at cs.uiuc.edu] On Behalf Of Jonas Paulsson
Sent: Monday, February 11, 2013 11:16 AM
To: llvmdev at cs.uiuc.edu<mailto:llvmdev at cs.uiuc.edu>
Subject: [LLVMdev] DFAPacketizer

Hi,

I am having problems writing the ProcessorItineraries list. As instructions on my VLIW target have varying size I want to model both cpu units and bundle bits as FUs. The following does not work, to my surprise:

InstrItinData<ALU,  [InstrStage<1, [BITS1,BITS2, BITS3, BITS4], 0>,
                               InstrStage<1, [ALU1, ALU2]>]>

I want to express that there are two ALU's, and four bundle slots, and in this case while allocating this type of instructions several times, I would like to be allowed only two such instructions per cycle.

ResourceTracker->reserveResources();
ResourceTracker->reserveResources();
ResourceTracker->reserveResources();
ResourceTracker->reserveResources();
ResourceTracker->reserveResources();
DFAPacketizer.cpp:84: void llvm::DFAPacketizer::reserveResources(const llvm::MCInstrDesc*): Assertion `CachedTable.count(StateTrans) != 0' failed.

It seems to not want to worry about the alu's, but it is fine as long as there are any FU of the first row (BITS) available.

What is missing?

Thanks,

Jonas Paulsson

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