[LLVMdev] Emulating an infinite register file in the backend

[nkavv at physics.auth.gr]

Hi Justin,

> The original PTX back-end just didn't perform register allocation.  All
> registers emitted in the assembly were virtual registers, mapped to a
> consecutive range.  E.g., %vreg7, %vreg13, and %vreg72 might be emitted as
> %r0, %r1, %r2.

OK, I see.

>> I'm (just starting) implementing an LLVM target that bares some
>> similarities to PTX. One of these is the notion of infinite registers,
>> since my target too is a kind of virtual/universal machine.
>>
>
> It's a bit of an uphill battle since there are places in LLVM that make
> assumptions about targeting a "real" architecture, to varying degrees.  One
> thing to keep in mind is that the PTX back-end from 3.1 may be a better
> example to use than the NVPTX back-end in 3.2 and TOT.  The original PTX
> back-end supported less (and is therefore a bit simpler), and it also
> doesn't suffer from as much backwards-compatibility cruft.  NVPTX has
> evolved over many LLVM revisions, and sometimes uses old techniques.  I'm
> working on getting it up to date.

Are you going to re-introduce the PTX backend in LLVM 3.3? I will  
certainly check PTX in LLVM 3.1 in order to draw some comparisons.


Best regards,
Nikolaos Kavvadias