[LLVMdev] Trouble with instructions for lowering load/store.

[EARL]

Hello.
I write backend for Z80 cpu and I have some trouble with lowering 
load/store nodes to different machine opcodes. Some target instructions 
work with specified registers (not all registers in RegisterClass). 
Often it's one or two registers. I don't understand how use 
ComplexPattern in this case. But if I don't use ComplexPattern I'll have 
other problems - not all instruction can select in InstructionSelection 
pass.

My work place here: https://github.com/earl1k/llvm-z80

Example of some load instructions for Z80 CPU with opcode:
Opcode          Instruction             node pattern
0x46               LD $dst,(HL)        (set GR8:$dst, (load HL))
0x0A              LD A,(BC)             (set A, (load BC))
0x1A              LD A,(DE)             (set A, (load DE))
0x3A              LD A,($src)           (set A, (load i16imm:$src))

Target Description file:
...
let canFoldAsLoad = 1, isReMaterializable = 1 in {
   let Uses = [HL] in
   def LD8rm : IRy<0x46, (outs GR8:$dst), (ins),
     "ld\t{$dst, (hl)}", [(set GR8:$dst, (load HL))]>;
   let Defs = [A], Uses = [BC] in
   def LD8AmBC : I<0x0A, (outs), (ins),
     "ld\t{a, (bc)}", [(set A, (load BC))]>;
   let Defs = [A], Uses = [DE] in
   def LD8AmDE : I<0x1A, (outs), (ins),
     "ld\t{a, (bc)}", [(set A, (load DE))]>;
   let Defs = [A] in
   def LD8Am : II16<0x3A, (outs), (ins i16imm:$src),
     "ld\t{a, ($src)", [(set A, (load imm:$src))]>;
}
...


GR8 - i8 RegisterClass (contains registers: A, B, C, D, E, H, L)
GR16 - i16 RegisterClas (contains registers: BC, DE, HL)

I have some questions:
1. Can I specify the register in TargetLowering or SelectionDAGISel and 
how do it?
2. How most effectively and correctly define target instructions?

Thanks.