[LLVMdev] Question about Pre-RA-schedule in LLVM3.3

[Haishan]

Hi,
  I compile a case (test.c) to get object machine file (test.o) using clang as follows:
  "clang -target arm -integrated-as -c test.c -o test.o"
My clang version is 3.3 and debug build.


//test.c
int a[6] = {1, 2, 3, 4, 5, 6}
int main() {
  a[0] = a[5];
  a[1] = a[4];
  a[2] = a[5];
}
//end test.c
Then test.dump is generated by using the objdump tool.
//test.dump
ldr  r1, [r0, #20]
str  r1, [r0]
ldr  r1, [r0, #16]
str  r1, [r0, #4]
ldr  r1, [r0, #12]
str  r1, [r0, #8]
bx  lr
//end test.dump
From the test.dump, we can see that the first instruction and second one use a register "r1", the 3th and 4th use the same register "r1", it's same to the 5th and 6th instruction.
That's to say, the six instructions use the same register.
However, for 3th and 4th instructions, they should be allocated different register from the second instruction.
So, I insert a breakpoint in BuildSchedGraph function in ScheduleDAGSNodes.cpp to debug the source code.
Then I get schedule graph of this basic block:
Like the above graph,  Pre-RA-sched(ScheduleRRList.cpp) is unable to insert the 3th SDNode(load2 instruction) between the first SDNode(load1 Instruction) and the second store1 SDNode.
Then in the register allocation step, the pair instruction are allocated same register.
However, if we build a schedule graph like the following:


I think that Pre-RA-sched has change to schedule apart load1 and store1, the same to load2 and store2.
Have someone considered building such a schedule graph?
Thank you very much if any suggestion.
-Haishan
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