[LLVMdev] Reflexions about a new HDL language

[Jonas Baggett]

Hi,

For the synthesis backend which translate to VHDL or Verilog, I don't 
know if I will use LLVM. It will depend on how easy it is to play with 
concurrent statements with LLVM. For the simulation I will use LLVM 
because I can anyways artificially make the compiled code sequencial. It 
would allow me to benefit from all the nice things from LLVM like 
existing optimisations. I have never used LLVM, I just read a litlle the 
documentation and the tutorial.

Cheers,
Jonas


Le 30. 08. 13 11:24, Óscar Fuentes a écrit :
> Jonas Baggett<jonasb at tranquille.ch>  writes:
>
>> What are your feedbacks ?
> Hello Jonas,
>
> How is that related to LLVM? I see no references to LLVM on your
> announcement nor on your document.