[LLVMdev] vector type legalization

[Redmond, Paul]

Hi Nadav,

On 2013-08-12 12:59 PM, "Nadav Rotem" <nrotem at apple.com> wrote:

>Hi Paul, 
>
>You can read about it here:
>http://blog.llvm.org/2011/12/llvm-31-vector-changes.html
>
>> Hi,
>> 
>> I am trying to understand how vector type legalization works. In
>>particular, I'm looking at i8 vector types on x86 (with sse42 features)
>> 
>> v3i8 gets widened to v4i8 and then operations get unrolled (scalarized)
>>because v4i8 is not a legal type whereas v4i8 gets
>
>This does not sound right.   v3i8 -> v4i8 is okay. But the next step
>should be v4i8 -> v4i32.  The operation nay be scalarized in the vector
>legalization phase.

What I'm looking at is a v3i8 add. In DAGTypeLegalizer::WidenVecRes_Binary
the operation gets scalarized (DAG.UnrollVector). The input N is
"0x51c1d60: v3i8 = add 0x51c1860, 0x51c1c60 [ORD=5] [ID=0]" and the
WidenVT is v4i8. The code ends up in the NumElts == 1 path which causes
scalarization.

The debug dump shows "Widen node result 0: 0x563dd20: v3i8 = add
0x563d820, 0x563dc20 [ORD=5] [ID=0]". To me it doesn't look like it's
possible to both widen and promote an operation..

Paul

>
>> promoted to v4i32. Why doesn't v3i8 (or even v4i8) get widened to
>>v16i8? Alternatively, v3i8 could be widened to v4i8 then promoted to
>>v4i32 but this doesn't happen either.
>> 
>> Can anyone provide some insight into why vector type legalization works
>>the way it does?
>> 
>> Thanks,
>> paul
>> 
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>