[LLVMdev] [global-isel] Type-independence of load/store

Tim Northover t.p.northover at gmail.com
Fri Aug 9 05:12:33 PDT 2013

Hi Jakob,

Sounds like a really exciting topic; I'd love to be involved in
implementation. I've not really had time to think about the
implications of the larger picture, but one detail did strike me on
the first read-through:

> On the other hand, when types are not used to select register banks, it
> becomes really difficult to explain the difference between load i32 and load
> f32. The hardware doesn't care either, it simply knows how to load 32 bits
> into a given register.

> We can use a three-level hierarchical type system to
> better describe this:

That may be something we want to be flexible about. I know we don't
support big-endian ARM at the moment, but its NEON load/store
instructions do take an interest in more than just the total number of
bits I think.

        vst1.16 {d0}, [r0]
        vst1.64 {d0}, [r0]
would give byte-wise layouts of
        1 0 3 2 5 4 7 6
        7 6 5 4 3 2 1 0

Other big-endian targets may have similar issues, but I know virtually
nothing about them.

Of course, if those three categories are just helpful mental models
(perhaps with convenience functions) then there's likely no issue. We
probably shouldn't go around discarding the "irrelevant" information



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